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AT80SND1C-ROTIL Arkusz danych(PDF) 14 Page - ATMEL Corporation |
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AT80SND1C-ROTIL Arkusz danych(HTML) 14 Page - ATMEL Corporation |
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14 / 210 page ![]() 14 AT8xC51SND1C 4109E–8051–06/03 Figure 9. PLL Filter Connection PLL Programming The PLL is programmed using the flow shown in Figure 10. As soon as clock generation is enabled, the user must wait until the lock indicator is set to ensure the clock output is stable. The PLL clock frequency will depend on MP3 decoder clock and audio interface clock frequencies. Figure 10. PLL Programming Flow VSS FILT R C1 C2 VSS PLL Programming Configure Dividers N6:0 = xxxxxxb R9:0 = xxxxxxxxxxb Enable PLL PLLRES = 0 PLLEN = 1 PLL Locked? PLOCK = 1? |
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