AT80SND1C-ROTIL datasheet(49/210 Pages) ATMEL

49 / 210 page

AT8xC51SND1C

4109E–8051–06/03

resumes when the input is released (see Figure 26) while using KINx input,

execution resumes after counting 1024 clock ensuring the oscillator is

restarted properly (see Figure 27). This behavior is necessary for decoding

the key while it is still pressed. In both cases, execution resumes with the

interrupt service routine. Upon completion of the interrupt service routine,

program execution resumes with the instruction immediately following the

instruction that activated Power-down mode.

Note:

1. The external interrupt used to exit Power-down mode must be configured as level

sensitive (

INT0 and INT1) and must be assigned the highest priority. In addition, the

duration of the interrupt must be long enough to allow the oscillator to stabilize. The

execution will only resume when the interrupt is deasserted.

2. Exit from power-down by external interrupt does not affect the SFRs nor the internal

RAM content.

Figure 26. Power-down Exit Waveform Using INT1:0

Figure 27. Power-down Exit Waveform Using KIN3:0

Note:

1. KIN3:0 can be high or low-level triggered.

Generate a reset.

–

A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU

and peripherals. Program execution momentarily resumes with the

instruction immediately following the instruction that activated Power-down

mode and may continue for a number of clock cycles before the internal

reset algorithm takes control. Reset initializes the AT8xC51SND1C and

vectors the CPU to address 0000h.

Notes:

1. During the time that execution resumes, the internal RAM cannot be accessed; how-

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at

the Port pins, the instruction immediately following the instruction that activated the

Power-down mode should not write to a Port pin or to the external RAM.

2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal

RAM content.

INT1:0

OSC

Power-down Phase

Oscillator Restart Phase

Active Phase

Active phase

KIN3:0

OSC

Power-down Phase

1024 clock count

Active phase

AT80SND1C-ROTIL Arkusz danych(PDF) 49 Page - ATMEL Corporation

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