AT80SND1C-ROTIL datasheet(53/210 Pages) ATMEL

53 / 210 page

AT8xC51SND1C

4109E–8051–06/03

Mode 1 (16-bit Timer)

Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in

cascade (see Figure 31). The selected input increments TL0 register. Figure 32 gives

the overflow period calculation formula when in timer mode.

Figure 31. Timer/Counter x (x = 0 or 1) in Mode 1

Figure 32. Mode 1 Overflow Period Formula

Mode 2 (8-bit Timer with Auto-

Reload)

Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

from TH0 register (see Table 62). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next

reload value may be changed at any time by writing it to TH0 register. Figure 34 gives

the autoreload period calculation formula when in timer mode.

Figure 33. Timer/Counter x (x = 0 or 1) in Mode 2

Figure 34. Mode 2 Autoreload Period Formula

Mode 3 (2 8-bit Timers)

Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit

Timers (see Figure 35). This mode is provided for applications requiring an additional 8-

bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-

ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a

Timer function (counting F

TF1/6) and takes over use of the Timer 1 interrupt (TF1) and

run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

Overflow

Timer x

Interrupt

Request

C/Tx#

TMOD Reg

TLx

(8 bits)

THx

(8 bits)

INTx

TIMx

CLOCK

÷ 6

⋅ (65536 – (THx, TLx))

TFxPER=

TIMx

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

Overflow

Timer x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(8 bits)

THx

(8 bits)

INTx

TIMx

CLOCK

÷ 6

TFxPER=

TIMx

⋅ (256 – THx)

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