| Zakładka z wyszukiwarką danych komponentów |
|
TDA9103 Arkusz danych(PDF) 12 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
TDA9103 Arkusz danych(HTML) 12 Page - STMicroelectronics |
|
12 / 27 page ![]() The dynamic behaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A ”CRC” filter is generally used. PLL1 is inhibited by applying a high level on Pin 35 (PLLinhib) which is a TTL compatible input. The inhibi- tion results from the opening of a switch located be- tween the charge pump and the filter (see Figure 8). The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and dis- charge of the capacitor, by a current proportionnal to the current in the resistor. typical thresholds of sawtooth are 1.6V and 6.4V. 12 PLL1F Figure 9 C Lockdet LOCKDET COMP1 INPUT INTERFACE CHARGE PUMP PLL INHIBITION VCO PHASE ADJUST Eini Horizontal Adjust R0 C0 Filter Horizontal Input High Low E2 3.2V OSC 17 13 35 12 11 10 15 Figure 8 : Principle Diagram The control voltage of the VCO is typically com- prised between 1.6V and 6V. The theoretical fre- quency range of this VCO is in the ratio 1 → 3.75, but due to spread and thermal drift of external components and the circuit itself, the effective fre- quency range has to be smaller (e.g. 30kHz → 82kHz). In the absenceof synchronisationsignal the control voltage is equal to 1.6V typ. and the VCO oscillates on its lowest frequency (free frequency). The synchro frequencyhas to be always higher than the free frequency and a margin has to be taken. As an example for a synchro range from 30kHz to 82kHz, the suggested free frequency is 27kHz. To compensate for the spread of external components and of the circuit itself, the free frequency may be adjusted by a DC voltage on Pin 14 (Fmin adjust) (see Figure10 for details). The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage adjustable between 2.4V and 4V (by Pin 15). So a ±45° phase adjustment is possible. 11 12 14 Loop Fil ter R0 (0.8V < a < 1.2V) FHMINADJ 1.6V 6.4V 10 C0 6.4V 1.6V 0 0.75T T RS FLIP FLOP a (1.6V < V < 6V) 12 I0 I0 2 4I0 2 Figure 10 : Details of VCO and Fhmin Adjustment TDA9103 12/27 |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |