| Zakładka z wyszukiwarką danych komponentów |
|
TDA9103 Arkusz danych(PDF) 17 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
TDA9103 Arkusz danych(HTML) 17 Page - STMicroelectronics |
|
17 / 27 page ![]() + Analog. Multiplier E/W-CENT E/W-AMP Vertical Ramp or I 38 37 36 Figure 21 : Parabola Generation Principle PARABOLA GENERATION FOR EAST-WEST CORRECTION (see Figure 21) Starting from the vertical ramp a parabola is gen- erated for E/W correction. The core of the parabola generator is an analog multiplier which generates a current in the form : I= k (VRAMP -VMID) 2 Where VRAMP is the vertical ramp, typically com- prised between 2 and 5V, VMID is a DC voltage with a nominal value of 3.5V, but adjustable in the range 3.2V → 3.8V in order to generate a dissymmetric parabola if required (keystone adjustment). The current is converted into voltage through a variable gain transresistance amplifier. The gain, controlled by the voltage on Pin 37 (E/W-AMP) can be adjusted in the ratio 3/1. The parabola is available on Pin 36 by the way of an emitter follower which has to be biased by an external resistor (10k Ω). It must be AC coupled with external circuitry. The typical parabola amplitude (AC), with the DC control voltages V37 and V38 set to 4V, is 2V. It is important to note that the parasitic parabola during the discharge of the vertical oscillator ca- pacitor is suppressed. VERTICAL PART (see Figure 22) The vertical part generates a fixed amplitude ramp which can be affected by a S correction shape. Then, the amplitude of this ramp is adjusted to drive an external power stage. The internal reference voltage used for the vertical part is available between Pin 26 and Pin 24. It can be used as voltage reference for any DC adjusment to keep a high accuracy to each adjustment. Its typical value is : V26 =VREF =8V. The charge of the external capacitor on Pin 27 (VCAP) generates a fixed amplitude ramp between the internal voltages, VL (VL =VREF/4) and VH (VH = 5/8 ⋅ VREF). V REF Osc Cap R 19R Sampling Cap V REF S Correction VERT-OUT VERT-AMP Parabola Generator EW-AMP KEYST EW-OUT OSCIL SYNCHRO V-SYNC Disch. Charge Current Transconductance Amplifier 27 25 34 38 37 36 31 30 28 29 S-CENTER S-AMP Figure 22 : Vertical Part Block Diagram TDA9103 17/27 |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |