TDA9103 datasheet(14/27 Pages) STMICROELECTRONICS

14 / 27 page

C Lockdet

LOCKDET

COMP1

INPUT

INTERFACE

CHARGE

PUMP

PLL

INHIBITION

VCO

PHASE

ADJUST

Eini

Horizontal

Adjust

R0 C0

Filter

Freq

Adjust

High

Low

3.2V

OSC

FAJUST

HFREQ

GENPULSE

COMP2

CHARGE

PUMP

High

Low

RAP

CYC

Adjust

Rapcyc

Cap

PH12

PWM

LOGI

PWM

BUFFER

FLYBACK

SortCOLL

Flyback

SortEM

Horizontal

Input

11 10

Figure 14 : Dual PLL Block Diagram

PLL2

The PLL2 ensures the coincidence between the

leading edge of the shaped flyback signal and a

phase reference signal obtained by comparison of

the sawtooth of the VCO and a constant DC voltage

(3.2V) (see Figure 15).

The phase comparator of PLL2 is similar to the one

of PLL1, it is followed by a charge pump with a

20k

Ω

400

Ω

GND 0V

HFLY

Figure 16 : Flyback Input Electrical Diagram

H Osc

Sawtooth

Phase REF2

H Drive

1.6V

3.2V

6.4V

0.75T

0.25T

Duty Cycle

Shapped

Flyback

Phase REF2 is obtained by comparison between the sawtooth and

a 3.2V (constant). The PLL2 ensures the exact

coincidence

between the signals phase REF2 and the flyback signal. The duty

cycle of H-drive is adjustable between 30% and 50%.

Figure 15 : PLL2 Timing Diagram

±0.5mA (typ.) output current.

The flyback input is composed of an NPN transistor.

This input has to be current driven. The maximum

recommanded input current is 2mA (see Fig-

ure 16).

Output Section

The H-drive signal is transmitted to the output

through a shaping block ensuring a duty cycle

adjustable from 30% to 50%. In order to ensure a

reliable operation of the scanning power part, the

output is inhibited in the following circumstances :

-VCC too low.

- Xray protection activated.

- During the flyback.

- Output voluntarily inhibited.

The output stage is composed of a Darlington NPN

bipolar transistor. Both the collector and the emitter

are accessible.

TDA9103

14/27

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