SPC5702BECLU datasheet(5/98 Pages) FREESCALE

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Overview

MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

1.2

MPC5606S Features

•

Single issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z0h)

— Compatible with classic PowerPC instruction set

— Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of

mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over

conventional Book E compliant code

•

On-chip ECC flash memory with flash controller

— Up to 1 MB primary flash—two 512 KB modules with prefetch buffer and 128-bit data access port

— 64 KB data flash—separate 4

×16 KB flash block for EEPROM Emulation with prefetch buffer and 128-bit data

access port

•

Up to 48 KB on-chip ECC SRAM with SRAM controller

•

Up to 160 KB on-chip non-ECC graphics SRAM with SRAM controller

•

Memory protection unit (MPU) with up to 12 region descriptors and 32-byte region granularity to provide basic

memory access permission

•

Interrupt controller (INTC) with up to 127 peripheral interrupt sources and eight software interrupts

•

Two frequency-modulated phase-locked loops (FMPLLs)

— Primary FMPLL provides a 64 MHz system clock

— Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS

modules and as alternate clock to the DCU for pixel clock generation

•

Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus

masters (AMBA 2.0 v6 AHB)

•

16-channel enhanced direct memory access controller (eDMA) with multiple transfer request sources using a DMA

channel multiplexer

•

Boot assist module (BAM) for embedded boot code supports boot options including download of code via a serial link

(CAN or SPI)

•

Display control unit to drive TFT LCD displays. It includes processing of up to four planes that can be blended together

and offers a direct un-buffered hardware bit-blitter of up to 16 software-configurable dynamic layers in order to

drastically minimize graphic memory requirements and provide fast animations. Programmable display resolutions are

available up to WVGA.

•

Parallel Data Interface for digital video input

•

The LCD segment driver module has two software programmable configurations:

— Up to 40 front plane drivers and 4 backplane drivers

— Up to 38 frontplane drivers and 6 backplane drivers

•

Stepper Motor Controller module with high-current drivers for up to six instrument cluster gauges driven in full dual

H-Bridge configuration including full diagnostics for short circuit detection

•

Stepper motor return-to-zero and stall detection module

•

Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and polyphonic sound

•

24 eMIOs channels providing up to 16 PWM and 24 input capture / output compare channels

•

10-bit analog-to-digital converter (ADC) with a maximum conversion time of 1

μs

— 16 internal channels

— Extendable to eight multiplexed external channels

•

Up to three DSPI (Deserial Serial Peripheral Interface) modules for full-duplex, synchronous, communications with

external devices

•

QuadSPI serial flash memory controller supporting single, dual and quad modes of operation to interface to external

serial flash memory or optionally can be configured to function as another DSPI module (MPC5606S only)

•

Two Local Interconnect Network (LIN) controller modules capable of autonomous message handling (master),

autonomous header handling (slave mode), and UART support. Compliant with LIN protocol rev 2.1

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