SPC5702BECLU datasheet(79/98 Pages) FREESCALE

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Electrical Characteristics

MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

•

DCU_HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.

•

DCU_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

•

DCU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display.

When disabled, the data is invalid and the trace is off.

Figure 26. TFT LCD InterfaceTiming Overview1

3.16.3.1

Interface to TFT LCD Panels—Pixel Level Timings

Figure 27 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and data. All parameters

shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DCU_CLK signal

(meaning the data and sync signals change on the rising edge) and active-high polarity of the DCU_HSYNC, DCU_VSYNC

and DCU_DE signals. The user can select the polarity of the DCU_HSYNC and DCU_VSYNC signals via the SYN_POL

Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are programmed via the DCU

Clock Confide Register (DCCR) in the system clock module.

The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H and FP_H

parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the

VSYN_PARA register.

1. In Figure 26, the “DCU_LD[23:0]” signal is an aggregation of the DCU’s RGB signals—DCU_R[0:7], DCU_G[0:7] and

DCU_B[0:7].

Table 37. LCD Interface Timing Parameters—Horizontal and Vertical

Num

Symbol

Characteristic

Value

Unit

1tPCP

CC1

Display pixel clock period

31.25

2tPWH

CC1

HSYNC pulse width

PW_H * tPCP

3tBPH

CC1

HSYNC back porch width

BP_H * tPCP

4tFPH

CC1

HSYNC front porch width

FP_H * tPCP

5tSW

CC1

Screen width

DELTA_X * tPCP

LINE 1

LINE 2

LINE 3

LINE 4

LINE n-1

LINE n

DCU_VSYNC

DCU_HSYNC

DCU_DE

DCU_CLK

DCU_LD[23:0]

m-1

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