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LTC6906CS6 Arkusz danych(PDF) 10 Page - Linear Technology |
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LTC6906CS6 Arkusz danych(HTML) 10 Page - Linear Technology |
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10 / 12 page ![]() LTC6906 10 6906fa APPLICATIO S I FOR ATIO Start-Up Time When the LTC6906 is powered up, it holds the OUT pin low. After the master oscillator has settled, the OUT pin is enabled and the first output cycle is guaranteed to be within specification. The time from power-up to the first output transition is given approximately by: tSTART ≅ 64 • tOSC + 100µs The digital divider ratio, N, does not affect the start-up time. Power Supply Rejection The LTC6906 has a very low supply voltage coefficient, meaning that the output frequency is nearly insensitive to the DC power supply voltage. In most cases, this error term can be neglected. High frequency noise on the power supply (V+) pin has the potential to interfere with the LTC6906’s master oscillator. Periodic noise, such as that generated by a switching power supply, can shift the output frequency or increase jitter. The risk increases when the fundamental frequency or harmonics of the noise fall near the master oscillator frequency. It is relatively easy to filter the LTC6906 power supply because of the very low supply current. For ex- ample, an RC filter with R = 160 Ω and C = 10µF provides a 100Hz lowpass filter while dropping the supply voltage only about 10mV. Operating the LTC6906 with Supplies Higher Than 3.6V The LTC6906 may also be used with supply voltages between 3.6V and 5.5V under very specific conditions. To ensure proper functioning above 3.6V, a filter circuit must be attached to the power supply and located within 1cm of the device. A simple RC filter consisting of a 100 Ω resistor and 1 µF capacitor (Figure 16) will ensure that supply resonance at higher supply voltages does not induce Figure 12. Test Circuit with an Inductive Power Supply Figure 13. Output Waveforms with an Inductive Supply (See Figure 12) Figure 14. Test Circuit with a Resistive Power Supply Figure 15. Output Waveforms with a Resistive Supply (See Figure 14) V+ GND DIV OUT GRD SET LTC6906 RSET 100k LS 330nH 3.3V 6906 F12 CLOAD 1MHz V+ GND DIV OUT GRD SET LTC6906 RSET 100k RS 100 Ω 3.3V 6906 F14 CLOAD 1MHz TIME ( µs) 4.65 2 3 5.05 6906 F13 1 0 4.75 4.85 5.15 3.5 4.95 CLOAD = 5pF CLOAD = 10pF CLOAD = 20pF CLOAD = 50pF TIME ( µs) 0.4 2 3 1.0 6906 F15 1 0 0.7 0.6 0.5 0.8 1.1 3.5 0.9 CLOAD = 5pF CLOAD = 10pF CLOAD = 20pF CLOAD = 50pF |
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