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LTC6906CS6 Arkusz danych(PDF) 5 Page - Linear Technology |
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LTC6906CS6 Arkusz danych(HTML) 5 Page - Linear Technology |
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5 / 12 page ![]() LTC6906 5 6906fa PI FU CTIO S OUT (Pin 1): Oscillator Output. The OUT pin swings from GND to V+ with an output resistance of approximately 150 Ω. For micropower operation, the load resistance must be kept as high as possible and the load capacitance as low as possible. GND (Pin 2): Ground. DIV (Pin 3): Divider Setting Input. This three-level input selects one of three internal digital divider settings, deter- mining the value of N in the frequency equation. Tie to GND for ÷1, leave floating for ÷3 and tie to V+ for ÷10. When left floating, the LTC6906 pulls Pin 3 to mid-supply with a 2.5M resistor. When Pin 3 is floating, care should be taken to reduce coupling from the OUT pin and its trace to Pin 3. Coupling can be reduced by increasing the physical space between traces or by shielding the DIV pin with grounded metal. SET (Pin 4): Frequency Setting Resistor Input. Connect a resistor, RSET, from this pin to GND to set the oscillator frequency. For best performance use a precision metal- or thin-film resistor of 0.5% or better tolerance and 50ppm/ °C or better temperature coefficient. For lower accuracy applications, an inexpensive 1% thick-film resistor may be used. Limit the capacitance in parallel with RSET to less than 10pF to reduce jitter and to ensure stability. Capaci- tance greater than 10pF could cause the LTC6906 internal feedback circuits to oscillate. The voltage on the SET pin is approximately 650mV and decreases with temperature by about –2.2mV/ °C. GRD (Pin 5): Guard Signal. This pin can be used to reduce PC board leakage across the frequency setting resistor, RSET. The GRD pin is held within a few millivolts of the SET pin and shunts leakage current away from the SET pin. To control leakage, connect a bare copper trace (a trace with no solder mask) to GRD and loop it around the SET pin and all PC board metal connected to SET. V+ (Pin 6): Voltage Supply (2.25V to 3.6V). This supply is internally decoupled with a 20 Ω resistor in series with an 800pF capacitor. No external decoupling capacitor is required for OUT pin loads less than 50pF. V+ should be kept reasonably free of noise and ripple. BLOCK DIAGRA 4 6 1 OP AMP fOSC 150 Ω DRIVER fOSC IFB IFB OUT 6906 BD 3 DIV PROGRAMMABLE DIVIDER (n) ( ÷1, ÷3, ÷10) THREE-LEVEL INPUT DETECTOR VOLTAGE CONTROLLED OSCILLATOR (MASTER OSCILLATOR) fOSC = 1MHz • 100kΩ/RSET SET V+ 2 GND 20 Ω 800pF VSET ≅ VGRD ≅ 650mV ISET = IFB FREQUENCY-TO-CURRENT CONVERTERS DECOUPLING NETWORK BUFFER GRD RSET 5M 5M DIVIDER SELECT V+ VSET VSET VSET 5 |
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