ACT8332

Rev0, 14-Mar-08

Innovative Power

TM

- 4 -

www.active-semi.com

Copyright © 2008 Active-Semi, Inc.

ActivePMU

PIN DESCRIPTIONS

PIN

NAME

DESCRIPTION

1

VP1

Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close as

possible to the IC.

2

SW1

Switching node Output for REG1. Connect this pin to the switching end of the inductor.

3

GP1

Power Ground for REG1. Connect GA, GP1 together at a single point as close to the IC as

possible.

4

OUT2

Output voltage for REG2. Capable of delivering up to 360mA of output current. Output has

high impedance when disabled.

5

INL

Power input for REG2, REG3. Bypass to GA with a high quality ceramic capacitor placed as

close as possible to the IC.

6

OUT3

Output voltage for REG3. Capable of delivering up to 360mA of output current. Output has

high impedance when disabled.

7

GA

Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1 together at a

single point as close to the IC as possible.

8

ON1

Enable control input for REG1, REG2. Drive ON1 to the VP1 or a logic high for normal

operation, drive to GA or a logic low to disable REG1, REG2

9

ON3

Enable control input for REG3. Drive ON3 to the INL or a logic high for normal operation, drive

to GA or a logic low to disable REG3

10

FB1

Output Feedback Sense. For fixed output voltage options REG1, connect this pin directly to

the output node to connect the internal feedback network to the output voltage. For adjustable

output voltage Options REG1. The voltage at this pin is regulated to 0.625V. Connect this pin

to the center point of the output voltage feedback network between OUT1 and GA to set the

output voltage.

EP

EP

Exposed Pad. Must be soldered to ground on PCB