ACT8332 datasheet(12/13 Pages) ACTIVE-SEMI

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ACT8332

Rev0, 14-Mar-08

LOW-DROPOUT LINEAR REGULATORS

Innovative Power

- 12 -

www.active-semi.com

ActivePMU

TM is a trademark of Active-Semi.

FUNCTIONAL DESCRIPTION

General Description

REG2 and REG3 are low-noise, low-dropout linear

regulators (LDOs) that are optimized for low-noise

and high-PSRR operation, achieving more than

60dB PSRR at frequencies up to 10kHz.

Output Current Capability

REG2 and REG3 each supply 360mA of load cur-

rent. Excellent performance is achieved over each

regulator's entire load current ranges.

Output Current Limit

In order to ensure safe operation under over-load

conditions, each LDO features current-limit circuitry

with current fold-back. The current-limit circuitry

limits the current that can be drawn from the output,

providing protection in over-load conditions. For

additional protection under extreme over current

conditions, current-fold-back protection reduces the

current-limit by approximately 30% under extreme

overload conditions.

Enabling and Disabling the LDOs

REG2 and REG3 is enabled or disabled using ON1

and ON3. Drive ON1 and ON3 to a logic-high to

enable REG2 and REG3. Drive ON1 and ON3 to a

logic-low to disable REG2 and REG3, reducing

supply current to less than 1µA.

Output Capacitor Selection

REG2 and REG3 each require only a small ceramic

capacitor for stability. For best performance, each

output capacitor should be connected directly be-

tween the OUT2 and OUT3 and G pins as possible,

with a short and direct connection. To ensure best

performance for the device, the output capacitor

should have a minimum capacitance of 1µF, and

ESR value between 10mΩ and 200mΩ. High quality

ceramic capacitors such as X7R and X5R dielectric

types are strongly recommended.

PCB Layout Considerations

The ACT8332’s LDOs provide good DC, AC, and

noise performance over a wide range of operating

conditions, and are relatively insensitive to layout

considerations. When designing a PCB, however,

careful layout is necessary to prevent other circuitry

from degrading LDO performance.

A good design places input and output capacitors

as close to the LDO inputs and output as possible,

and utilizes a star-ground configuration for all regu-

lators to prevent noise-coupling through ground.

Output traces should be routed to avoid close prox-

imity to noisy nodes, particularly the SW nodes of

the DC/DCs.

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