AD7944BCPZ datasheet(16/28 Pages) AD

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AD7944

Rev. 0 | Page 16 of 28

Reference Decoupling

VOLTAGE REFERENCE INPUT

The AD7944 voltage reference input, REF, has a dynamic input

impedance that requires careful decoupling between the REF

and REFGND pins. The Layout section describes how this can

be done.

The AD7944 allows the choice of a very low temperature drift

internal voltage reference, an external reference, or an external

buffered reference.

The internal reference of the AD7944 provides excellent

performance and can be used in almost all applications.

When using an external reference, a very low impedance source

(for example, a reference buffer using the AD8031 or the AD8605)

and a 10 μF (X5R, 0805 size) ceramic chip capacitor are appro-

priate for optimum performance.

Internal Reference, REF = 4.096 V (PDREF Low)

To use the internal reference, the PDREF input must be low.

This enables the on-chip band gap reference and buffer, result-

ing in a 4.096 V reference on the REF pin (1.2 V on REFIN).

If an unbuffered reference voltage is used, the decoupling value

depends on the reference used. For example, a 22 μF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR43x reference.

The internal reference is temperature compensated to

4.096 V ± 15 mV. The reference is trimmed to provide

a typical drift of 10 ppm/°C.

If desired, a reference decoupling capacitor with a value as small

as 2.2 μF can be used with minimal impact on performance,

especially DNL.

The output resistance of REFIN is 6 kΩ when the internal

reference is enabled. It is necessary to decouple this pin with a

ceramic capacitor of at least 100 nF. The output resistance of

REFIN and the decoupling capacitor form an RC filter, which

helps to reduce noise.

In any case, there is no need for an additional, lower value

ceramic decoupling capacitor (for example, 100 nF) between

the REF and REFGND pins.

Because the output impedance of REFIN is typically 6 kΩ,

relative humidity (among other industrial contaminants) can

directly affect the drift characteristics of the reference. A guard

ring is typically used to reduce the effects of drift under such

circumstances. However, the fine pitch of the AD7944 makes

this difficult to implement. One solution, in these industrial

and other types of applications, is to use a conformal coating,

such as Dow Corning® 1-2577 or HumiSeal® 1B73.

POWER SUPPLY

The AD7944 has four power supply pins: an analog supply

(AVDD), a buffer supply (BVDD), a digital supply (DVDD), and

a digital input/output interface supply (VIO). VIO allows a direct

interface to any logic from 1.8 V to 2.7 V. To reduce the number

of supplies needed, the VIO, DVDD, and AVDD pins can be

tied together. The power supplies do not need to be started in a

particular sequence. In addition, the AD7944 is very insensitive

to power supply variations over a wide frequency range.

External 1.2 V Reference and Internal Buffer (PDREF High)

To use an external reference along with the internal buffer, PDREF

must be high. This powers down the internal reference and allows

the 1.2 V reference to be applied to REFIN, producing 4.096 V

(typically) on the REF pin.

In normal mode, the AD7944 powers down automatically at

the end of each conversion phase and, therefore, the power

scales linearly with the sampling rate. This makes the part ideal

for low sampling rates (even of a few SPS) and battery-powered

applications.

External Reference (PDREF High, REFIN Low)

To apply an external reference voltage directly to the REF pin, tie

PDREF high and tie REFIN low. BVDD should also be driven to

the same potential as REF. For example, if REF = 2.5 V, BVDD

should be tied to 2.5 V.

0.1

0.01

0.1

SAMPLING RATE (MSPS)

The advantages of directly using an external voltage reference

are as follows:

•

SNR and dynamic range improvement (about 1.7 dB)

resulting from the use of a larger reference voltage (5 V)

instead of a typical 4.096 V reference when the internal

reference is used. This is calculated by

IBVDD

IAVDD

IDVDD

IVIO

⎟

⎠

⎞

⎜

⎝

⎛

096

log

SNR

IVREF

•

Power savings when the internal reference is powered

down (PDREF high).

Figure 25. Operating Current vs. Sampling Rate in Normal Mode

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