AD7944BCPZ datasheet(19/28 Pages) AD

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AD7944

Rev. 0 | Page 19 of 28

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7944 is connected

to an SPI-compatible digital host. The connection diagram is

shown in Figure 26, and the corresponding timing is given in

Figure 27.

With SDI tied to VIO, a rising edge on CNV initiates a con-

version, selects CS mode, and forces SDO to high impedance.

When a conversion is initiated, it continues until completion,

irrespective of the state of CNV. This can be useful, for example,

to bring CNV low to select other SPI devices, such as analog

multiplexers; however, CNV must be returned high before the

minimum conversion time elapses and then held high for the

maximum possible conversion time to avoid the generation of

the busy signal indicator.

When the conversion is complete, the AD7944 enters the

acquisition phase and, if the part is in normal mode (TURBO

low), powers down. When CNV goes low, the MSB is output

onto SDO. The remaining data bits are clocked by subsequent

SCK falling edges. The data is valid on both SCK edges. Although

the rising edge can be used to capture the data, a digital host

using the SCK falling edge allows a faster reading rate, provided

that it has an acceptable hold time. After the 14th SCK falling

edge or when CNV goes high (whichever occurs first), SDO

returns to high impedance.

CONVERT

DATA IN

CLK

DIGITAL HOST

AD7944

SDI

SDO

CNV

SCK

VIO

Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)

ACQUISITION (n)

ACQUISITION

(n + 1)

ACQUISITION

(n – 1)

BEGIN DATA (n – 1)

CONVERSION (n)

END DATA (n – 1)

SCK

CNV

SDO

CONVERSION (n – 1)

END DATA (n – 2)

tCONV

tDATA

(I/O QUIET

TIME)

(I/O QUIET

TIME)

SDI = 1

113

tCONV

(I/O QUIET

TIME)

tCYC

tACQ

tCNVH

tQUIET

tSCK

tHSDO

tDATA

tCONV

tDIS

tEN

tDSDO

Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)

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