AD7944BCPZ datasheet(21/28 Pages) AD

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AD7944

Rev. 0 | Page 21 of 28

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7944 devices are

connected to an SPI-compatible digital host. A connection dia-

gram example using two AD7944 devices is shown in Figure 30,

and the corresponding timing is given in Figure 31.

With SDI high, a rising edge on CNV initiates a conversion,

selects CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase

and the subsequent data readback. (If SDI and CNV are low,

SDO is driven low.) Prior to the minimum conversion time,

SDI can be used to select other SPI devices, such as analog multi-

plexers, but SDI must be returned high before the minimum

conversion time elapses and then held high for the maximum

possible conversion time to avoid the generation of the busy

signal indicator.

When the conversion is complete, the AD7944 enters the

acquisition phase and, if the part is in normal mode (TURBO

low), powers down. Each ADC result can be read by bringing its

SDI input low, which consequently outputs the MSB onto SDO.

The remaining data bits are then clocked by subsequent SCK

falling edges. The data is valid on both SCK edges. Although the

rising edge can be used to capture the data, a digital host using

the SCK falling edge allows a faster reading rate, provided that it

has an acceptable hold time. After the 14th SCK falling edge, SDO

returns to high impedance and another AD7944 can be read.

AD7944

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

CS1

CS2

AD7944

SDI

SDO

CNV

SCK

Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram

ACQUISITION (n)

ACQUISITION

(n – 1)

ACQUISITION

(n + 1)

BEGIN DATA (n – 1)

CONVERSION (n)

END DATA (n – 1)

SCK

SDO

CNV

CONVERSION (n – 1)

END DATA (n – 2)

tCONV

tDATA

(I/O QUIET

TIME)

(I/O QUIET

TIME)

(I/O QUIET

TIME)

113

SDI

tCYC

tACQ

tQUIET

tHSDICNV

tSSDICNV

tDATA

tCONV

tSCK

tDIS

tHSDO

tEN

tDSDO

tHSDO

Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing

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