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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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WM8170 Arkusz danych(PDF) 32 Page - Wolfson Microelectronics plc |
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WM8170 Arkusz danych(HTML) 32 Page - Wolfson Microelectronics plc |
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32 / 41 page  WM8170 Product Preview Rev 1.0 WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 32 DEVICE CONFIGURATION REGISTER MAP The register map is shown in Table 15. In Serial Mode the contents of address location <a5> determines whether the address location defined by <a[4:0]> is to be read from or written to. For a read operation <a5> is set to 1. To write to a register <a5> should be cleared to 0. In Parallel Mode a 0 in <a5> forces a write operation. A high level on RNW, irrespective of the contents of <a5>, however, determines a parallel read operation. BIT Address <a5:a0> Description Default (Hex) RW b7 b6 b5 b4 b3 b2 B1 b0 000000 Not Used 000001 Software Reset W 0 0 0 0 0 0 0 0 000010 Set Up Register 1 02 RW STOPDC 0 POSVID TIMES2 INVSHX ACINP VCLP1 VCLP0 000011 Set Up Register 2 00 RW PTDO2 PTDO1 PTDO0 INVDIG RETIME 0 0 0 000100 Black Level Target 40 RW TARGET7 TARGET6 TARGET5 TARGET4 TARGET3 TARGET2 TARGET1 TARGET0 000101 PGA Gain 00 RW GAIN7 GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 000110 Digital Duration 02 RW 0 0 0 0 DIGDUR3 DIGDUR2 DIGDUR1 DIGDUR0 000111 Analogue Duration 05 RW 0 ANDUR6 ANDUR5 ANDUR4 ANDUR3 ANDUR2 ANDUR1 ANDUR0 001000 Reserved 001001 Threshold Detect LSB 00 RW THRES7 THRES6 THRES5 THRES4 THRES3 THRES2 THRES1 THRES0 001010 Threshold Detect MSB 00 RW 0 0 0 0 0 0 THRES9 THRES8 001011 Power Down 1 00 RW 0 0 0 0 0 0 0 PDA 001100 Power Down 2 00 RW 0 0 PD5 PD4 PD3 PD2 PD1 PD0 001101 Auxiliary DAC1 00 RW AUX1 DAC7 AUX1 DAC6 AUX1 DAC5 AUX1 DAC4 AUX1 DAC3 AUX1 DAC2 AUX1 DAC1 AUX1 DAC0 001110 Auxiliary DAC2 00 RW AUX2 DAC7 AUX2 DAC6 AUX2 DAC4 AUX2 DAC4 AUX2 DAC3 AUX2 DAC2 AUX2 DAC1 AUX2 DAC0 001111 DC Correct Control 30 RW ACON1 ACON0 STPIIR STPANAL PGAUPD ENVD ENHD ENINTBLC 010000 AUX DAC Control 00 RW 0 0 0 0 0 0 AUX2X1 AUX1X1 010001 Analog Enable Delay 00 RW ANDEL7 ANDEL6 ANDEL5 ANDEL4 ANDEL3 ANDEL2 ANDEL1 ANDEL0 010010 Analog Enable Width 00 RW ANLINE7 ANLINE6 ANLINE5 ANLINE4 ANLINE3 ANLINE2 ANLINE1 ANLINE0 010011 INTBLCENB Delay 00 RW CLPDEL7 CLPDEL6 CLPDEL5 CLPDEL4 CLPDEL3 CLPDEL2 CLPDEL1 CLPDEL0 010100 INTBLCENB Width 00 RW CLPWID7 CLPWID6 CLPWID5 CLPWID4 CLPWID3 CLPWID2 CLPWID1 CLPWID0 010101 Area Line Delay LSB 00 RW LINDEL7 LINDEL6 LINDEL5 LINDEL4 LINDEL3 LINDEL2 LINDEL1 LINDEL0 010110 Area Line Delay MSB 00 RW LINDEL11 LINDEL10 LINDEL9 LINDEL8 010111 Reference Select 00 RW 0 0 0 0 0 0 0 V375 011000 Area Line Width LSB 00 RW LINWID7 LINWID6 LINWID5 LINWID4 LINWID3 LINWID2 LINWID1 LINWID0 011001 Area Line Width MSB 00 RW LINWID11 LINWID10 LINWID9 LINWID8 011010 Area Pixel Delay LSB 00 RW PIXDEL7 PIXDEL6 PIXDEL5 PIXDEL4 PIXDEL3 PIXDEL2 PIXDEL1 PIXDEL0 011011 Area Pixel Delay MSB 00 RW PIXDEL11 PIXDEL10 PIXDEL9 PIXDEL8 011100 Area Pixel Width LSB 00 RW PIXWID7 PIXWID6 PIXWID5 PIXWID4 PIXWID3 PIXWID2 PIXWID1 PIXWID0 011101 Area Pixel Width MSB 00 RW PIXWID11 PIXWID10 PIXWID9 PIXWID8 011110 IIR Filter Coefficient 00 RW COEFF2 COEFF1 COEFF0 011111 Revision Number R REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 Table 15 Register Table |
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