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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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XIO2001IPNP Arkusz danych(PDF) 74 Page - Texas Instruments |
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XIO2001IPNP Arkusz danych(HTML) 74 Page - Texas Instruments |
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74 / 131 page  XIO2001 SCPS212D – MAY 2009 – REVISED JANUARY 2010 www.ti.com Table 4-36. Control and Diagnostic Register 1 Description (continued) BIT FIELD NAME ACCESS DESCRIPTION 5:2(1) L0s_TIMER RW L0s entry timer. This field specifies the value (in 62.5-MHz clock ticks) of the L0s entry timer. This field defaults to 0010b. 1:0(1) RSVD RW Reserved. Bits 1:0 default to 00b. If this register is programmed via EEPROM or another mechanism, then the value written into this field must be 00b. 4.63 Control and Diagnostic Register 2 The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table 4-37 for a complete description of the register contents. It is recommended that all values within this register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems. PCI register offset: C8h Register type: Read/Write Default value: 3214 2000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-37. Control and Diagnostic Register 2 Description BIT FIELD NAME ACCESS DESCRIPTION 31:24(1) N_FTS_ RW N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h, see ASYNC_CLK Section 4.53) is clear, the value in this field is the number of FTS that are sent on a transition from L0s to L0. This field shall default to 32h. 23:16(1) N_FTS_ RW N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see Section 4.53) COMMON_ is set, the value in this field is the number of FTS that are sent on a transition from L0s to L0. This CLK field defaults to 14h. 15:13 PHY_REV R PHY revision number 12:8 (1) LINK_NUM RW Link number 7(1) EN_L2_PWR_ RW Enable L2 Power Savings SAVE 0= Power savings not enabled when in L2 1= Power savings enabled when in L2. 6 RSVD R Reserved. Returns 0b when read. 5(1) BAR0_EN RW BAR 0 Enable. 0 = BAR at offset 10h is disabled (default) 1 = BAR at offset 10h is enabled 4:0(1) RSVD RW Reserved. Bits 4:0 default to 00000b. If this register is programmed via EEPROM or another mechanism, then the value written into this field must be 00000b. (1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. 4.64 Subsystem Access Register The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 84h and 86h. See Table 4-38 for a complete description of the register contents. PCI register offset: D0h Register type: Read/Write Default value: 0000 0000h 74 Classic PCI Configuration Space Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): XIO2001 |
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