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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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XIO2001IPNP Arkusz danych(PDF) 20 Page - Texas Instruments |
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XIO2001IPNP Arkusz danych(HTML) 20 Page - Texas Instruments |
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20 / 131 page  XIO2001 SCPS212D – MAY 2009 – REVISED JANUARY 2010 www.ti.com Table 2-6. JTAG Terminals (continued) ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # PIN # TYPE TYPE RAIL PARTS JTAG_TRST L09 L09 60 I LV VDD_33 JTAG test reset. This terminal provides CMOS Optional for asynchronous initialization of the TAP controller. Note: This terminal has an internal Optional pullup active pullup resistor. The pullup is resistor active at all times. Note: This terminal should be tied to ground or pulled low if JTAG is not required. Table 2-7. Miscellaneous Terminals ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # PIN # TYPE TYPE RAIL PARTS CLKRUN_E A13 C11 96 I LV VDD_33 Clock run enable N CMOS 0 = Clock run support disabled Optional 1 = Clock run support enabled pullup resistor Note: The CLKRUN_EN input buffer has an internal active pulldown. This pulldown is active at all times. EXT_ARB_ C10 A12 97 I LV VDD_33 External arbiter enable EN CMOS 0 = Internal arbiter enabled Optional pullup 1 = External arbiter enabled resistor Note: The EXT_ARB_EN input buffer has an internal active pulldown. This pulldown is active at all times. GPIO0 // N09 N09 55 I/O LV VDD_33 General-purpose I/O 0/clock run. This terminal CLKRUN CMOS functions as a GPIO controlled by bit 0 (GPIO0_DIR) in the GPIO control register (see Section 4.59) or the clock run terminal. This terminal is used as clock run input when the bridge is placed in clock run mode. Optional pullup Note: In clock run mode, an external pullup resistor resistor is required to prevent the CLKRUN signal from floating. Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input. GPIO1 // M09 M09 56 I/O LV VDD_33 General-purpose I/O 1/power override. This PWR_OVR CMOS terminal functions as a GPIO controlled by bit 1 D (GPIO1_DIR) in the GPIO control register (see Section 4.59) or the power override output terminal. GPIO1 becomes PWR_OVRD when bits 22:20 (POWER_OVRD) in the general – control register are set to 001b or 011b (see Section 4.65). Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input. GPIO2 N10 N10 57 I/O LV VDD_33 General-purpose I/O 2. This terminal functions CMOS as a GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO control register (see Section 4.59). – Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input. 20 Overview Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): XIO2001 |
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