SA9101 datasheet(7/40 Pages) SAMES

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SA9101

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Clock Generator

Signal

Input/Output/Bidirect

Function

SCLK

System Clock f=4,096 MHz/8,192MHz

RFSPQ

Receive Frame Pulse

Frequency:

8 kHz

Duration: 488 ns

If loss of synchronisation, the line frame

pulse is inhibited

SYPQ

Synchronous Pulse

Defines start of frame for System internal

data, together with the programmed offset

values of transmit and receive counter.

Pulse width:

>244 ns

Period:

Multiples of 125µs

DIU Controller

Signal

Input/Output/Bidirect

Function

D0 - D7

7 - 14

Bidirectional 8 bit data-bus

A0 - A3

16 - 19

Address lines for SA9101 internal

registers

CEQ

Chip enable input

WRQ

Write enable input

RDQ

Read enable input

COS

Carrier out of service input.

SA9101 sends AIS to PCM30 interface

if input is at “1”

XREQ

Transmit DMA interrupt request

RREQ

Receive DMA interrupt request

AINT

Alarm interrupt request

ACKNLQ

DMA Acknowledge (Active Low)

(Not used when CR6B6 = 0. If not used

then pin must be fixed to V

DD.) If access to

internal TS16 signalling stacks is enabled

this input acts as an "access enable" to the

internal stacks (CRAB0-7 for T

and

SR7B0-7 for R

in conjunction with a

read/write command without the need of

generating the chip enable signal at CEQ.

In this case it is to be connected to the

acknowledge output of the DMA controller.

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