SST25WF080 datasheet(16/29 Pages) SST

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Advance Information

8Mbit 1.8V SPI Serial Flash

SST25WF080

S71203-03-000

04/10

Read-Status-Register (RDSR)

The Read-Status-Register (RDSR) instruction, 05H, allows

reading of the status register. The status register may be

read at any time even during a Write (Program/Erase)

operation. When a Write operation is in progress, the Busy

bit may be checked before sending any new commands to

assure that the new commands are properly received by

the device. CE# must be driven low before the RDSR

instruction is entered and remain low until the status data is

read. Read-Status-Register is continuous with ongoing

clock cycles until it is terminated by a low to high transition

of the CE#. See Figure 18 for the RDSR instruction

sequence.

FIGURE 18: Read-Status-Register (RDSR) Sequence

Write-Enable (WREN)

The Write-Enable (WREN) instruction, 06H, sets the Write-

Enable-Latch bit in the Status Register to 1 allowing Write

operations to occur. The WREN instruction must be exe-

cuted prior to any Write (Program/Erase) operation. The

WREN instruction may also be used to allow execution of

the Write-Status-Register (WRSR) instruction; however,

the Write-Enable-Latch bit in the Status Register will be

cleared upon the rising edge CE# of the WRSR instruction.

CE# must be driven high before the WREN instruction is

executed. See Figure 19 for the WREN instruction

sequence.

FIGURE 19: Write Enable (WREN) Sequence

1203 F17.0

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

HIGH IMPEDANCE

Status

MSB

CE#

SCK

01 2 3 4 5 6 7

HIGH IMPEDANCE

MODE 0

MODE 3

1203 F18.0

MSB

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