SST25WF080 datasheet(3/29 Pages) SST

3 / 29 page

Advance Information

8Mbit 1.8V SPI Serial Flash

SST25WF080

S71203-03-000

04/10

PIN DESCRIPTION

FIGURE 2: Pin Assignment for 8-Lead SOIC

FIGURE 3: Pin Assignment for 8-bump XFBGA

TABLE

1: Pin Description

Symbol

Pin Name

Functions

SCK

Serial Clock

To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock input,

while output data is shifted out on the falling edge of the clock input.

Serial Data Input

To transfer commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

Serial Data Output

To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.

Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See

“End-of-Write Detection” on page 12 for more information.

CE#

Chip Enable

The device is enabled by a high to low transition on CE#. CE# must remain low for the

duration of any command sequence.

WP#

Write Protect

The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.

RST#/HOLD#

Reset

To reset the operation of the device and the internal logic. The device powers on with

RST# pin functionality as default.

Hold

To temporarily stop serial communication with SPI Flash memory while device is

selected. This is selected by an instruction sequence; see “Reset/Hold Mode” on page 5.

VDD

Power Supply

To provide power supply voltage: 1.65-1.95V for SST25WF080

VSS

Ground

T1.0 1203

CE#

WP#

VSS

VDD

RST#/HOLD#

SCK

Top View

1203.25WF 08-soic-P0.0

Top View

(Balls Facing Down)

1328.25WF 8-xfbga P1.0

VSS

SCK

WP#

VDD

CE#

RST#/

HOLD#

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