Advance Information

8Mbit 1.8V SPI Serial Flash

SST25WF080

17

©2010 Silicon Storage Technology, Inc.

S71203-03-000

04/10

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction, 04H, resets the

Write-Enable-Latch bit and AAI to 0 disabling any new

Write operations from occurring. The WRDI instruction will

not terminate any programming operation in progress. Any

executing the WRDI instruction. CE# must be driven high

before the WRDI instruction is executed. See Figure 20 for

the WRDI instruction sequence.

FIGURE 20: Write Disable (WRDI) Sequence

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction

arms the Write-Status-Register (WRSR) instruction and

opens the status register for alteration. The Write-Status-

Register instruction must be executed immediately after the

execution of the Enable-Write-Status-Register instruction.

This two-step instruction sequence of the EWSR instruc-

tion followed by the WRSR instruction works like SDP (soft-

ware data protection) command structure which prevents

any accidental alteration of the status register values. CE#

must be driven low before the EWSR instruction is entered

and must be driven high before the EWSR instruction is

executed. See Figure 21 for EWSR instruction followed by

WRSR instruction.

Write-Status-Register (WRSR)

The Write-Status-Register instruction writes new values to

the BP3, BP2, BP1, BP0, and BPL bits of the status regis-

ter. CE# must be driven low before the command

sequence of the WRSR instruction is entered and driven

high before the WRSR instruction is executed. See Figure

21 for EWSR or WREN and WRSR instruction sequences.

Executing the Write-Status-Register instruction will be

ignored when WP# is low and BPL bit is set to ‘1’. When

the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to

lock-down the status register, but cannot be reset from ‘1’ to

‘0’. When WP# is high, the lock-down function of the BPL

bit is disabled and the BPL, BP0, BP1, BP2, and BP3 bits

in the status register can all be changed. As long as BPL bit

to-high transition of the CE# pin at the end of the WRSR

instruction, the bits in the status register can all be altered

by the WRSR instruction. In this case, a single WRSR

instruction can set the BPL bit to ‘1’ to lock down the status

register as well as altering the BP0, BP1, BP2, and BP3

bits at the same time. See Table 3 for a summary descrip-

tion of WP# and BPL functions.

FIGURE 21: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register

(WRSR) Sequence

CE#

SO

SI

SCK

01 2 3 4 5 6 7

04

HIGH IMPEDANCE

MODE 0

MODE 3

1203 F19.0

MSB

1203 F20.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

REGISTER IN

7 6 5 4321 0

MSB

MSB

MSB

01

MODE 3

SCK

SI

SO

CE#

MODE 0

50 or 06

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15