PCA9620 datasheet(39/71 Pages) NXP

39 / 71 page

PCA9620

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Product data sheet

Rev. 1 — 9 December 2010

39 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

Remark: In case that a external clock is used then this clock signal must always be

supplied to the device; removing the clock may freeze the LCD in a DC state, which is not

suitable for the liquid crystal. Removal of the clock is possible when following the correct

procedures. See Figure 12 on page 19 and Figure 13 on page 20.

7.5.3 Timing and frame frequency

The timing of the PCA9620 organizes the internal data flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. The

timing also generates the LCD frame frequency which it derives as an integer division of

the clock frequency. The frame frequency is a fixed division of the internal clock or of the

frequency applied to pin CLK when an external clock is used:

(13)

When the internal clock is used, the clock and frame frequency can be programmed by

software such that the nominal frame frequency can be chosen in steps of 10 Hz in the

range of 60 Hz to 300 Hz (see Table 17 on page 9). Furthermore the nominal frame

frequency is factory-calibrated with an accuracy of

±15 %.

When the internal clock is enabled at pin CLK by using bit COE, the duty ratio of the clock

may change when choosing different values for the frame frequency prescaler. Table 17

on page 9 shows the different output duty ratios for each frame frequency prescaler

setting.

7.6 Backplane outputs

The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane

output signals are generated based on the selected LCD multiplex drive mode.

Table 31 describes which outputs are active for each of the multiplex drive modes and

what signal is generated.

[1]

These pins may optionally be connected to the display to improve drive strength. Connect only with the

corresponding output pin carrying the same signal. If not required they can be left open-circuit.

clk

-------

Table 31.

Mapping of output pins and corresponding output signals with respect to the

multiplex driving mode

Multiplex

drive

mode

Output pin

BP0

BP1

BP2

BP3

BP4

BP5

BP6

BP7

Signal

1:8

BP0

BP1

BP2

BP3

BP4

BP5

BP6

BP7

1:6

BP0

BP1

BP2

BP3

BP4

BP5

BP0[1]

BP1[1]

1:4

BP0

BP1

BP2

BP3

BP0[1]

BP1[1]

BP2[1]

BP3[1]

1:2

BP0

BP1

BP0[1]

BP1[1]

BP0[1]

BP1[1]

BP0[1]

BP1[1]

static

BP0

BP0[1]

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