HT45B0F

Rev. 1.00

8

June 7, 2011

Bit 5

FERR: Framing error flag

0: no framing error is detected

1: framing error is detected

The FERR flag is the framing error flag. When this read only flag is

²0², it indicates that there

is no framing error. When the flag is

²1², it indicates that a framing error has been detected

for the current character. The flag can also be cleared by a software sequence which will involve

a read to the status register USR followed by an access to the RXR data register.

Bit 4

OERR: Overrun error flag

0: no overrun error is detected

1: overrun error is detected

The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed.

When this read only flag is

²0², it indicates that there is no overrun error. When the flag is

²1², it indicates that an overrun error occurs which will inhibit further transfers to the RXR

receive data register. The flag is cleared by a software sequence, which is a read to the status

register USR followed by an access to the RXR data register.

Bit 3

RIDLE: Receiver status

0: data reception is in progress (data being received)

1: no data reception is in progress (receiver is idle)

The RIDLE flag is the receiver status flag. When this read only flag is

²0², it indicates that the

receiver is between the initial detection of the start bit and the completion of the stop bit. When

the flag is

²1², it indicates that the receiver is idle. Between the completion of the stop bit and

the detection of the next start bit, the RIDLE bit is

²1² indicating that the UART receiver is idle

and the RX pin stays in logic high condition.

Bit 2

RXIF: Receive RXR data register status

0: RXR data register is empty

1: RXR data register has available data

The RXIF flag is the receive data register status flag. When this read only flag is

²0², it indicates

that the RXR read data register is empty. When the flag is

²1², it indicates that the RXR read data

register contains new data. When the contents of the shift register are transferred to the RXR

register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are

detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are

set within the same clock cycle. The RXIF flag is cleared when the USR register is read with

RXIF set, followed by a read from the RXR register, and if the RXR register has no data

available.

Bit 1

TIDLE: Transmission idle

0: data transmission is in progress (data being transmitted)

1: no data transmission is in progress (transmitter is idle)

The TIDLE flag is known as the transmission complete flag. When this read only flag is

²0²,it

indicates that a transmission is in progress. This flag will be set to

²1² when the TXIF flag is

²1² and when there is no transmit data or break character being transmitted. When TIDLE is

equal to

²1², the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is

cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag

is not generated when a data character or a break is queued and ready to be sent.

Bit 0

TXIF: Transmit TXR data register status

0: character is not transferred to the transmit shift register

1: character has transferred to the transmit shift register (TXR data register is empty)

The TXIF flag is the transmit data register empty flag. When this read only flag is

²0²,it

indicates that the character is not transferred to the transmitter shift register. When the flag is

²1², it indicates that the transmitter shift register has received a character from the TXR data

register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and

then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will

also be set since the transmit data register is not yet full.