HT45B0F

Rev. 1.00

11

June 7, 2011

Bit 3

WAKE: RX pin falling edge wake-up function enable control

0: RX pin wake-up function is disabled

1: RX pin wake-up function is enabled

This bit enables or disables the receiver wake-up function. If this bit is equal to

²1² and the

MCU is in IDLE or SLEEP mode, a falling edge on the RX input pin will through INT pin wake-up

the device. If this bit is equal to

²0² and the MCU is in IDLE or SLEEP mode,

any edge transitions on the RX pin will not wake-up the device.

Bit 2

RIE: Receiver interrupt enable control

0: receiver related interrupt is disabled

1: receiver related interrupt is enabled

This bit enables or disables the receiver interrupt. If this bit is equal to

²1² and when the

receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request

flag will be set. If this bit is equal to

²0², the UART interrupt request flag will not be influenced

by the condition of the OERR or RXIF flags.

Bit 1

TIIE: Transmitter Idle interrupt enable control

0: transmitter idle interrupt is disabled

1: transmitter idle interrupt is enabled

This bit enables or disables the transmitter idle interrupt. If this bit is equal to

²1² and when

the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt

request flag will be set. If this bit is equal to

²0², the UART interrupt request flag will not be

influenced by the condition of the TIDLE flag.

Bit 0

TEIE: Transmitter Empty interrupt enable control

0: transmitter empty interrupt is disabled

1: transmitter empty interrupt is enabled

This bit enables or disables the transmitter empty interrupt. If this bit is equal to

²1² and when

the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt

request flag will be set. If this bit is equal to

²0², the UART interrupt request flag will not be

influenced by the condition of the TXIF flag.

The UCR3 register is the last of the UART control registers and controls the software reset operation. The only one

available bit named URST in the UART control register UCR3 is the UART software reset control bit. When this bit is

equal to

²0², the UART operates normally. If this bit is equal to ²1², the whole HT45B0F will be reset. When this situa-

tion occurs, the transmitter and receiver will be reset. The UART registers including the status register and control

registers will keep the POR states shown in the above UART registers table after the reset condition occurs.

Bit

76543210

Name

URST

¾¾¾¾¾¾¾

R/W

R/W

¾¾¾¾¾¾¾

POR

0

¾¾¾¾¾¾¾

Bit 7

URST: UART software reset

0: no action

1: UART reset occurs

Bit 6~0

unimplemented, read as

²0²