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Zakładka z wyszukiwarką danych komponentów |
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MPC8569E Arkusz danych(PDF) 4 Page - Freescale Semiconductor, Inc |
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MPC8569E Arkusz danych(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 127 page  MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Ball Layout Diagrams Freescale Semiconductor 4 1 Pin Assignments and Reset States 1.1 Ball Layout Diagrams The following figure shows the top view of the MPC8569E 783-pin BGA ball map diagram. Figure 2. MPC8569E Top View Ballmap GVDD GND D2_ MCKE [3] D2_ MODT [1] D2_ MA [1] D2_ MA [11] D2_ MCS [1] D2_ MDQ [31] D2_ MDQ [30] D2_ MDM [3] D2_ MDQ [7] D2_ MDQ [29] D2_ MDQ [6] D2_ MDM [0] D2_ MDQ [5] D2_ MA [15] D2_ MA [4] GVDD GND D2_ MDQ [27] GVDD GND D2_ MDQ [28] D2_ MDQ [3] GVDD GND D2_ MDQ [0] D2_ MODT [0] D2_ MCKE [2] GVDD GND D2_ MCK [2] D2_ MCK [2] D2_ MDQ [26] D2_ MDQ [25] D2_ MDQS [3] D2_ MDQ [24] D2_ MDQ [2] D2_ MDQS [0] D2_ MDQS [0] D2_ MDQ [1] GVDD GND D2_ MA [13] GVDD GND D2_ MA [14] D2_ MECC [7] D2_ MECC [5] D2_ MDQS [3] GVDD GND D2_ MDQ [14] D2_ MDM [1] D2_ MDQ [13] D2_ MODT [3] D2_ MWE D2_ MCS [0] D2_ MA [0] D2_ MA [8] D2_ MBA [2] D2_ MECC [6] D2_ MDM [8] D2_ MCK [0] D2_ MCK [0] D2_ MDQ [15] GVDD GND D2_ MDQ [12] D2_ MAPAR_ OUT GVDD GND D2_ MBA [1] GVDD GND D2_ MECC [3] GVDD GND D2_ MECC [4] D2_ MDQ [11] D2_ MDQS [1] D2_ MDQ [9] D2_ MDQ [8] D2_ MAPAR_ ERR D2_ MCS [3] D2_ MA [6] D2_ MRAS D2_ MA [9] D2_ MA [3] D2_ MCKE [0] D2_ MECC [2] D2_ MDQS [8] D2_ MDQS [1] GND GVDD D2_ MODT [2] D2_ MA [5] GVDD GND D2_ MCS [2] D2_ MECC [1] D2_ MDQS [8] GVDD GND D2_ MDQ [23] GVDD GND D2_ MVREF D2_ MDIC [0] GVDD D2_ MCAS D2_ MBA [0] D2_ MA [10] D2_ MA [2] D2_ MA [7] D2_ MA [12] D2_ MCK [1] D2_ MCK [1] D2_ MDQ [19] D2_ MDQS [2] D2_ MDQ [17] AVDD_ CE GND GVDD GVDD GND GVDD GND D2_ MCKE [1] GVDD GVDD GVDD GND D2_ MDQ [18] D2_ MDIC [1] AVDD_ CORE QE_PC [3] QE_PA [22] QE_PA [18] QE_PA [15] QE_PC [16] GND GND QE_PB [18] QE_PB [12] GND VDD GND GND GND LVDD2 QE_PA [23] QE_PA [20] QE_PA [16] LVDD2 QE_PC [17] QE_PB [19] LVDD2 QE_PB [13] VDD GND VDD GVDD GND VDD GND VDD GND GND GND GND GND GND GND VDD VDD VDD VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND GND SENSE- VDD SENSE- VSS QE_PA [24] QE_PA [28] QE_PC [2] QE_PA [26] QE_PA [21] QE_PA [17] GND QE_PC [24] QE_PB [20] GND QE_PB [14] QE_PA [19] QE_PB [17] QE_PC [25] QE_PB [9] QE_PB [1] QE_PA [29] QE_PA [14] QE_PB [24] QE_PB [21] QE_PB [16] QE_PB [15] QE_PA [25] QE_PB [23] QE_PC [9] LVDD1 QE_PB [0] LVDD1 QE_PC [11] QE_PA [12] QE_PA [6] QE_PA [4] QE_PA [2] QE_PA [27] QE_PB [22] QE_PB [3] GND QE_PA [31] GND QE_PC [8] QE_PA [8] GND LVDD1 QE_PA [0] QE_PE [22] QE_PE [14] QE_PE [16] QE_PE [11] QE_PE [10] QE_PE [17] QE_PB [25] QE_PB [4] QE_PB [5] QE_PB [6] QE_PA [30] QE_PC [20] QE_PA [9] QE_PA [7] QE_PA [3] QE_PA [1] QE_PB [7] QE_PB [8] QE_PB [10] QE_PB [2] QE_PC [29] QE_PA [13] QE_PA [11] QE_PA [10] QE_PA [5] QE_PC [5] QE_PC [0] QE_PC [1] QE_PC [6] OVDD QE_PC [7] QE_PC [26] QE_PC [27] OVDD QE_PB [11] OVDD QE_PC [22] QE_PC [23] QE_PC [19] GND QE_PC [4] QE_PD [18] QE_PD [26] GND QE_PD [21] GND QE_PC [13] QE_PC [15] QE_PC [14] QE_PC [12] QE_PD [24] QE_PD [19] QE_PD [17] QE_PD [27] QE_PD [22] QE_PD [20] QE_PC [31] QE_PC [30] QE_PC [21] QE_PC [10] QE_PC [18] QE_PE [15] QE_PD [10] QE_PD [6] QE_PD [15] QE_PD [16] OVDD QE_PD [25] QE_PD [23] QE_PE [25] QE_PE [26] LDP [0] QE_PE [12] QE_PE [13] QE_PE [18] QE_PD [11] BVDD QE_PD [8] QE_PD [14] QE_PB [28] GND QE_PF [10] QE_PF [11] QE_PE [24] QE_PF [4] LCS [3] QE_PE [21] QE_PE [19] QE_PE [20] QE_PD [5] GND QE_PD [9] QE_PD [7] QE_PB [29] QE_PB [30] QE_PB [31] QE_PF [12] QE_PF [9] QE_PF [5] LCS4_ IRQ [8] QE_PE [23] OVDD QE_PE [5] QE_PD [4] QE_PD [12] QE_PD [13] QE_PE [31] QE_PF [2] QE_PF [16] QE_PF [15] OVDD QE_PF [7] QE_PF [3] LA [18] QE_PD [28] GND QE_PE [4] QE_PE [2] QE_PD [3] QE_PD [1] OVDD QE_PF [0] QE_PF [17] QE_PF [18] GND QE_PF [6] QE_PC [28] LAD [1] QE_PD [29] QE_PD [30] QE_PE [6] QE_PE [3] QE_PE [9] QE_PD [2] GND QE_PF [1] QE_PF [21] QE_PE [28] QE_PE [30] QE_PF [8] QE_PB [26] LAD [0] QE_PD [31] QE_PE [0] QE_PE [1] QE_PE [8] QE_PE [7] QE_PD [0] QE_PF [20] QE_PF [19] QE_PF [22] QE_PE [29] QE_PE [27] QE_PF [13] QE_PF [14] QE_PB [27] D1_ MCKE [3] D1_ MDIC [1] D1_ MA [1] D1_ MA [11] D1_ MDIC [0] D1_ MDQ [31] D1_ MDQ [30] D1_ MDM [3] D1_ MDQ [29] D1_ MDQ [7] D1_ MA [13] D1_ MDQ [6] D1_ MDM [0] D1_ MDQ [5] D2_ MDQ [4] GVDD GND D1_ MA [4] GVDD GND D1_ MDQ [27] GVDD GND D1_ MDQ [28] D1_ MDQ [3] GVDD GND D1_ MDQ [4] D1_ MA [15] D1_ MODT [0] D1_ MCKE [2] D1_ MA [6] D1_ MCK [2] D1_ MCK [2] D1_ MDQ [26] D1_ MDQ [25] D1_ MDQS [3] D1_ MDQ [24] D1_ MDQ [2] D1_ MDQS [0] D1_ MDQ [1] D1_ MDQ [0] GVDD GND D1_ MA [14] D1_ MCS [0] GVDD GND D1_ MECC [7] D1_ MECC [5] D1_ MDQS [3] GVDD GND D1_ MDQS [0] GVDD GND D1_ MAPAR_ OUT D1_ MODT [3] D1_ MWE D1_ MA [0] D1_ MA [8] D1_ MBA [2] D1_ MECC [6] D1_ MDM [8] D1_ MCK [0] D1_ MCK [0] D1_ MDQ [15] D1_ MDQ [14] D1_ MDM [1] D1_ MDQ [13] D1_ MAPAR_ ERR GVDD GND D1_ MBA [1] GVDD GND D1_ MECC [3] GVDD GND D1_ MECC [4] D1_ MDQ [11] GVDD GND D1_ MDQ [12] D2_ MDQ [21] D1_ MCS [3] D1_ MODT [2] D1_ MRAS D1_ MA [9] D1_ MA [3] D1_ MCKE [0] D1_ MECC [2] D1_ MDQS [8] D1_ MECC [0] D1_ MDQ [10] D1_ MDQS [1] D1_ MDQ [9] D1_ MDQ [8] D2_ MDQ [20] GVDD GND D1_ MA [5] D1_ MA [2] GVDD GND D1_ MECC [1] D1_ MDQS [8] GVDD GND D1_ MDQS [1] GVDD GND D2_ MDQ [16] D1_ MODT [1] D1_ MCAS D1_ MA [10] GVDD D1_ MCKE [1] D1_ MA [7] D1_ MA [12] D1_ MCK [1] D1_ MCK [1] D1_ MDQ [23] D1_ MDQ [22] D1_ MDM [2] D1_ MDQ [21] GND D1_ MCS [1] D1_ MBA [0] GVDD GND D1_ MCS [2] GND GVDD D1_ MDQ [18] D1_ MDQS [2] D1_ MDQ [19] GVDD GND D1_ MDQ [20] GND GVDD GND GVDD GND D1_ MDQS [2] D1_ MDQ [17] D1_ MDQ [16] GND IRQ_ OUT UDE MCP ASLEEP CLK_ OUT RTC OVDD GND AVDD_ DDR IRQ4_ MSRCID [3] TCK TMS OVDD GND TRIG_IN BVDD_ VSEL [0] D1_ MVREF AVDD_ PLAT BVDD_ VSEL [1] TDI TRST TDO TRIG_OUT_ _READY__ QUIESCE SYSCLK LVDD_ VSEL [1] GND GND IRQ [0] IRQ5_ MSRCID [4] IRQ6_ DVAL XVDD XGND IRQ [3] IRQ [2] SCORE- VDD SCORE- GND GND IRQ [1] Rsvd SD_TX [0] SD_TX [0] SCORE- GND SCORE- VDD SD_RX [0] SD_RX [0] Rsvd Rsvd GND XVDD XGND AGND_ SRDS AVDD_ SRDS SCORE- GND SCORE- VDD GND XVDD XGND SD_TX [1] SD_TX [1] SCORE- GND SCORE- VDD SD_RX [1] SD_RX [1] GND SD_PLL_ TPD SD_IMP_ CAL_RX XGND XVDD SD_REF_ CLK SD_REF_ CLK SCORE- VDD SCORE- GND GND XGND XVDD SD_TX [2] SD_TX [2] SCORE- VDD SCORE- GND SD_RX [2] SD_RX [2] LDP [1] LGPL [5] LGPL1_ LFALE LGPL4_ LUPWAIT_ LBPBSE_ LFRB LGPL0_ LFCLE LGPL3_ LFWP SD_TX_ CLK XVDD XGND SD_IMP_ CAL_TX SD_PLL_ TPA SCORE- GND SCORE- VDD GND LCS [1] BVDD LCS [0] BVDD LA [25] BVDD LCS7_ IRQ [11] XVDD XGND SRESET HRESET_ REQ SCORE- VDD SCORE- GND LCS [2] GND LWE1_ LBS [1] GND LWE0_ LBS0_ LFWE XVDD XGND SD_TX [3] SD_TX [3] XGND SCORE- GND SD_RX [3] SD_RX [3] LA [16] LA [17] LA [19] LA [21] LA [23] LGPL2_ LOE_ LFRE LAD [15] LCS6_ IRQ [10] HRESET DMA_ DACK2_ SD_CMD DMA_ DDONE_ [0] DMA_ DREQ2_ SD_DAT0 DMA_ DACK1_ MSRCID1 LVDD_ VSEL [0] LBCTL LA [20] LA [22] LA [24] LA [26] LAD [13] LAD [12] LA [27] LCS5_ IRQ [9] DMA_ DDONE1_ MSRCID2 DMA_ DREQ1_ MSRCID0 GND OVDD CKSTP_ IN BVDD LCLK [1] BVDD LCLK [0] BVDD LAD [7] BVDD LAD [14] DMA_ DACK_ [0] OVDD DMA_ DDONE2_ SD_WP IIC2_ SCL_SD_ CD UART_ SIN0_DMA _DACK3_ SD_DAT2 CKSTP_ OUT GND LAD [2] GND LAD [6] GND LAD [8] GND LAD [11] DMA_ DREQ_ [0] GND IIC2_ SDA_SD_ CLK IIC1_ SCL UART_ CTS0_DMA _DDONE3_ SD_DAT3 UART_ SOUT0_DMA _DREQ3_ SD_DAT1 LSYNC_ OUT LSYNC_ IN LAD [3] LAD [4] LAD [5] LALE LAD [9] LAD [10] GND AVDD_ LBIU GND IIC1_ SDA LSSD_ MODE UART_ RTS [0] OVDD D2_ MECC [0] D2_ MDQ [10] D2_ MDQ [22] D2_ MDM [2] SD_TX_ CLK D2_ MDQS [2] 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 18 19 20 21 22 23 24 25 26 27 28 W Y AA AB AC AD AE AF AG AH A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 18 A B C D E F G H J K L M N P R T U V 19 20 21 22 23 24 25 26 27 28 SEE DETAIL A SEE DETAIL B SEE DETAIL D SEE DETAIL C |
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