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MPC8569E Arkusz danych(PDF) 72 Page - Freescale Semiconductor, Inc |
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MPC8569E Arkusz danych(HTML) 72 Page - Freescale Semiconductor, Inc |
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72 / 127 page ![]() MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Ethernet Interface Freescale Semiconductor 72 2.6.5 QUICC Engine Block IEEE 1588 Electrical Characteristics 2.6.5.1 QUICC Engine Block IEEE 1588 DC Specifications The following table shows the QUICC Engine block IEEE 1588 DC specifications when operating from a 3.3 V supply. 2.6.5.2 QUICC Engine Block IEEE 1588 AC Specifications The following table provides the QUICC Engine block IEEE 1588 AC timing specifications. Table 40. QUICC Engine Block IEEE 1588 DC Electrical Characteristics At recommended operating conditions with OVDD =3.3 V Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 1 Input low voltage VIL —0.90 V — Input high current (VIN = OVDD)IIH —40 μA2 Input low current (VIN = GND) IIL –600 — μA2 Output high voltage (OVDD = min, IOH = –4.0 mA) VOH 2.1 OVDD + 0.3 V — Output low voltage (OVDD = min, IOL = 4.0 mA) VOL GND 0.50 V — Note: 1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3. 2. The symbol VIN, in this case, represents the OVIN symbols referenced in Table 2 and Table 3. Table 41. QUICC Engine Block IEEE 1588 AC Timing Specifications Parameter Symbol Min Typ Max Unit Notes QE_1588_CLK clock period tT1588CLK 3.8 — TRX_CLK × 7 ns 1, 3 QE_1588_CLK duty cycle tT1588CLKH/ tT1588CLK 40 50 60 % 5 QE_1588_CLK peak-to-peak jitter tT1588CLKINJ —— 250 ps 5 Rise time QE_1588_CLK (20%–80%) tT1588CLKINR 1.0 — 2.0 ns 5 Fall time QE_1588_CLK (80%–20%) tT1588CLKINF 1.0 — 2.0 ns 5 QE_1588_CLK_OUT clock period tT1588CLKOUT 2×tT1588CLK —— ns — QE_1588_CLK_OUT duty cycle tT1588CLKOTH/ tT1588CLKOUT 30 50 70 % — QE_1588_PPS_OUT tT1588OV 0.5 — 4.0 ns — |
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