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33813 Arkusz danych(PDF) 31 Page - Freescale Semiconductor, Inc |
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33813 Arkusz danych(HTML) 31 Page - Freescale Semiconductor, Inc |
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31 / 54 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 31 33813 5.1.27 Input Comparator Threshold Values The threshold voltage for the input comparator is produced by a 4-bit D/A converter. The control of the D/A output value is by means of the upper four bits of the SPI VRS configuration register or the upper four bits of the SPI VRS control register. When the contents of the SPI VRS control register contains all zeros, the binary value for the D/A threshold is taken from the value in the SPI VRS configuration register. When the contents of the SPI VRS control register is non-zero, then the value in the upper four bits of the SPI VRS control register is used to set the D/A output. The values outputted by this D/A, using either the SPI VRS control register or the SPI VRS Configuration register, are listed in Table 11 in the threshold values table. The blanking one-shot time is also set via the lower 4 bits of the SPI VRS configuration register or the SPI VRS control register using the same condition, as described previously for the threshold D/A. 5.1.28 Blanking Time Definitions The values for the one shot blanking, as a percentage of the last high output pulse period is shown in Table 12. 5.1.29 Manual and Automatic Modes The SPI VRS miscellaneous configuration register has a bit to enable the automatic selection of the comparator threshold (bit 7). At this time, the operation of automatic mode remains TBD. 5.1.30 VRS Peak Detector The VRS peak detector determines the magnitude of the positive peak of the VRS input signal and digitizes it. The value of the VRS peak voltage is reported in the VRS SPI status register bits 7, 6, 5, and 4. The MCU can read the value of peak voltage after the zero crossing time of the input pulse, and uses this information to set the threshold and blanking parameters for subsequent input pulses. Status bits reflect the last detected peak and only read 0000 after a POR or SPI reset command. Table 12. SPI VRS Manual Configuration Register SPI VRS Configuration/Control Register Bits 3,2,1,0 Blanking Time in% (of last pulse high period) 0000 (default) 0.0 0001 3.12 0010 6.25 0011 9.37 0100 12.5 0101 15.62 0110 18.75 0111 21.87 1000 25 1001 28.1 1010 31.3 1011 34.4 1100 37.5 1101 40.6 1110 43.8 1111 46.9 |
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