33813 datasheet(17/54 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

33813

ALL LOW SIDE DRIVERS (CONTINUED)

Propagation Delay (Input Falling Edge OR CSB to Output Rising Edge)

• Input at 50%VDD to Output voltage 10% of VLOAD (INJ1, ROUT1, ROUT2,

LAMP)

tPLH

–

1.0

5.0

µs

Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)

• Input at 50%VDD to Output voltage 10% of VLOAD (TACHOMETER)

tPLH

–

1.0

6.0

µs

Output Slew Rate, Tachout

•RLOAD = 500 VLOAD = 14 V

tSR(FALL)

6.0

–

s

ALL GATE PRE-DRIVER (IGN1 AND O2H)

Output OFF Open-circuit Fault Filter Timer

t(OFF)OC

100

–

400

µs

Over-current (short-circuit) Fault Filter Timer

tSC

–

µs

Propagation Delay (Input Rising Edge OR CSB to Output Rising Edge)

• Input at 50%VDD to Output voltage 10% of VGS(ON)

tPLH

–

1.0

5.0

µs

Propagation Delay (Input Falling Edge OR CSB to Output Falling Edge)

• Input at 50%VDD to Output voltage 90% of VGS(ON)

tPHL

–

1.0

5.0

µs

SPI DIGITAL INTERFACE TIMING (16)

Falling Edge of CSB to Rising Edge of SCLK

• Required Setup Time

tLEAD

100

–

Falling Edge of SCLK to Rising Edge of CSB

• Required Setup Time

tLAG

–

SI to Rising Edge of SCLK

• Required Setup Time

tSI(SU)

–

Rising Edge of SCLK to SI

• Required Hold Time

tSI(HOLD)

–

SI, CSB, SCLK Signal Rise Time (17)

tR(SI)

–

5.0

–

SI, CSB, SCLK Signal Fall Time (17)

tF(SI)

–

5.0

–

Time from Falling Edge of CSB Low-impedance (18)

tSO(EN)

–

Time from Rising Edge off CSB to SO High-impedance (19)

tSO(DIS)

–

Time from Falling Edge of SCLK to SO Data Valid (20)

tVALID

–

Sequential Transfer Rate

• Time required between data transfers

tSTR

–

1.0

µs

Notes

16.

These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.

17.

Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent occurrence of double pulsing.

18.

Time required for valid output status data to be available on SO pin.

19.

Time required for output states data to be terminated at SO pin.

20.

Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.

Table 5. Dynamic Electrical Characteristics (15)

Characteristics noted under conditions of 6.0 V

 VPWR  18 V, -40 C  TC  125 C, and Calibrated Timers, unless otherwise

noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

Characteristic

Symbol

Min

Typ

Max

Unit

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