33813 datasheet(32/54 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

33813

5.1.31 VRS Deglitching Filters

The VRS input circuit has additional filters on the rising and falling edges of the input waveforms to reduce the effect of short

transitions that may occur during those noise sensitive times. The deglitching filters are approximately 1% of the last positive

pulse period. The deglitch filters are enabled by setting the deglitch bit (bit 3) in the SPI VRS miscellaneous parameters

configuration register. This bit is, by default, zero (0), meaning that the deglitch filters are disabled.

5.1.32 High/Low Reference Bit

The High/Low reference bit in the SPI VRS miscellaneous configuration register is used to change the use of the input high pulse

timing to input low pulse timing, in cases where an elongated tooth wheel is being used rather than the missing tooth wheel. The

default for this bit is zero (0), indicating the use of a crankshaft wheel with a missing tooth (or teeth).

5.1.33 Disable VRS Bit

The disable VRS bit in the SPI VRS miscellaneous configuration register is used to disable the VRS input circuitry when there is

no need for a VRS input conditioning circuit. This would be the case, for example, if the crankshaft wheel sensor was a hall effect

device whose output could be directly input to the MCU. The default for this bit is zero (0) indicating that the VRS input

conditioning circuitry is active.

Table 13. Peak Detector Output in SPI VRS Status Register

SPI VRS Status Register

Bits 7,6,5,4

Peak Values (nominal)

0000 (default)

10 mV

0001

14 mV

0010

20 mV

0011

28 mV

0100

40 mV

0101

56 mV

0110

80 mV

0111

113 mV

1000

159 mV

1001

225 mV

1010

318 mV

1011

450 mV

1100

636 mV

1101

900 mV

1110

1.273 V

1111

1.800 V

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