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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TNETX3100PGC Arkusz danych(PDF) 8 Page - Texas Instruments |
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TNETX3100PGC Arkusz danych(HTML) 8 Page - Texas Instruments |
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8 / 80 page  TNETX3100 ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS031D – JUNE 1997 – REVISED OCTOBER 1997 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (ports 00–01) (continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION M00TXD0 156 M01TXD0 178 M00TXD1 157 Transmit data Nibble transmit data is from the TNETX3100 When MXXTXEN is asserted these M01TXD1 179 O Transmit data. Nibble transmit data is from the TNETX3100. When MXXTXEN is asserted, these terminals carry transmit data. Data on these terminals is always synchronous to MXXTCLK. If M00TXD2 158 O yy y MWIDTH bit in the port control register and M00SPEED terminal are set low, then data is transmitted on M00TXD0 and M01TXD0 M01TXD2 180 on M00TXD0 and M01TXD0. M00TXD3 159 M01TXD3 181 M00TXEN 160 O Transmit enable. High = valid transmit data on MXXTXD and low = no valid transmit data on M01TXEN 182 O g MXXTXD. M00TXER 161 O Transmit error. MXXTXER allows coding errors to propagate across the MII. This enables external logic to reconstruct and resend the frame MXXTXER is asserted during an underrunning frame M01TXER 183 O logic to reconstruct and resend the frame. MXXTXER is asserted during an underrunning frame, enabling the TNETX3100 to force a coding error. DRAM interface TERMINAL I/O DESCRIPTION NAME† NO. I/O DESCRIPTION DA00 52 DA01 53 DA02 55 DA03 56 O DRAM address bus DA00 DA07 is time multiplexed with row and column address strobes DA04 57 O DRAM address bus. DA00–DA07 is time multiplexed with row and column address strobes. DA05 58 DA06 59 DA07 60 DX00 61 DRAM t d d dd li DX00 DX02 ti lti l d ith d l dd DX01 62 O DRAM extended address lines. DX00–DX02 are time multiplexed with row and column address strobes. DX02 64 strobes. DCAS 121 O DRAM column address select DRAS 120 O DRAM row address select † DD00 is the least-significant bit. |
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