2–2

DOUT is released from the high-impedance state on the falling edge of the primary or secondary frame-sync

interval. In addition, each register can be read back during DOUT secondary communications by setting the

read bit D13 to 1 in the appropriate register. When the register is in the read mode, no data can be written

to the register during this cycle. To return this register to the write mode requires a subsequent secondary

communication.

2.1.6

Sigma-Delta ADC

The sigma-delta ADC is a fourth-order sigma-delta modulator with 64 times oversampling. The ADC

provides high resolution and low noise performance using oversampling techniques.

2.1.7

Decimation Filter

The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating

with a ratio of 1:64. The output of this filter is a sixteen-bit 2’s-complement data word clocking at the sample

rate selected.

NOTE

The sample rate is determined through a relationship of MCLK/512.

2.1.8

Sigma-Delta DAC

The sigma-delta DAC is a fourth-order sigma-delta modulator with 64 times oversampling. The DAC

provides high-resolution, low-noise performance from a 1-bit converter using oversampling techniques. The

TLC320AD56C is a current-output DAC and requires a load resistor for current-to-voltage conversion (see

Figures 3–7 and 3–8).

2.1.9

Interpolation Filter

The interpolation filter resamples the digital data at a rate of 64 times the incoming sample rate. The

high-speed data output from this filter is then used in the sigma-delta DAC.

2.1.10

Digital Loopback

The digital loopback provides a means of testing the ADC/DAC channels and can be used for in-circuit

system-level tests. The loopback feeds the ADC output to the DAC input on the IC.

Digital loopback is enabled by setting the appropriate bit in Control 1 register (see Appendix A).

2.1.11

FIR Overflow Flag

The decimator FIR filter provides an overflow flag to the Control 2 register to indicate that the input to the

filter has exceeded the range of the internal filter calculations. When this bit is set in the register, it will remain

set until the register is read by the user. Reading this value will always reset the overflow flag.

2.2

Terminal Functions

The terminal functions are described in the following sections.

2.2.1

Reset and Power-Down Functions

2.2.1.1

Reset

The TLC320AD56C resets the internal counters and registers, including the programmed registers, in one

of two ways:

1.

By applying a low-going reset pulse to the reset terminal

2.

By writing to the programmable software reset bit (D07 in Control 1 register)

PWRDWN resets the counters only and preserves the programmed register contents. The PWRDWN

terminal must be kept low 20 ms after the power supplies have settled.