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TLC320AD56 Arkusz danych(PDF) 7 Page - Texas Instruments

Numer części TLC320AD56
Szczegółowy opis  Sigma-Delta Analog Interface Circuit
PDF  42 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

TLC320AD56 Arkusz danych(HTML) 7 Page - Texas Instruments

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1 Introduction
The TLC320AD56C provides high resolution low-speed signal conversion from digital-to-analog (D/A) and
from analog-to-digital (A/D) using oversampling sigma-delta technology. This device consists of two serial
synchronous conversion paths (one for each data direction) and includes an interpolation filter before the
digital-to-analog converter (DAC) and a decimation filter after the analog-digital-converter (ADC) (see
Figure 1–1). Other overhead functions provide on-chip timing and control. The sigma-delta architecture
produces high resolution A/D and D/A conversion at low system speeds and low cost.
The options and the circuit configurations of this device can be programmed through the serial interface.
The options include reset, power-down, communications protocol, serial clock rate, and test mode as
outlined in Appendix A. The TLC320AD56C is characterized for operation from 0
°C to 70°C.
1.1
Features
The TLC320AD56C includes the following features:
Single 5-V power supply voltage or 5 V analog and 3 V digital supply voltages
Power dissipation (PD) of 150 mW maximum in the operating mode
Power-down mode to 2.5 mW typical
General-purpose 16-bit signal processing
2’s-complement data format
Typical dynamic range of 85 dB for the DAC and 87 dB for the ADC
Minimum 79-dB total signal-to-(noise + distortion) for the ADC
Minimum 80-dB total signal-to-(noise + distortion) for the DAC
Differential architecture throughout the device
Internal reference voltage (Vref)
Internal 64X oversampling
Serial port interface
Phone-mode output control
System test mode, digital loopback test mode
Capable of supporting all V.34 sample rates by varying MCLK frequency
Supports business audio applications
Variable conversion rate selected as MCLK/512



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