TLC320AD56 datasheet(39/42 Pages) TI1

39 / 42 page

A–1

Appendix A

Bits D12 through D8 in a secondary serial communication comprise the address of the register that is written

with the data carried in D7 through D0. D13 determines a read or write cycle to the addressed register. When

low, a write cycle is selected.

Table A–1 shows the register map.

Table A–1. Data and Control Registers

BITS

D15

D14

D13

D12

D11

D10

No operation

000000

Control 1

Control 2

Table A–2. Control 1 Register

BITS

DESCRIPTION

–

Software reset

–

Software reset not asserted

–

Software power down (analog and filters)

–

Software power down (not asserted)

–

Select AUXP and AUXM

–

Select INP and INM

–

Select INP and INM for monitor

–

Select AUXP and AUXM for monitor

–

Monitor amp gain = – 18 dB (see Note B)

–

Monitor amp gain = – 8 dB (see Note B)

–

Monitor amp gain = 0 dB (see Note B)

–

Monitor amp mute

–

Digital loopback asserted

–

Digital loopback not asserted

–

16-bit mode (hardware secondary requests)

–

Not 16-bit mode (software secondary requests)

NOTES:

A. Default value: 00000000

B. These gains are for a single-ended input. The gain is 6 dB lower with a differential input.

The software reset is a one-shot operation and this bit is cleared to 0 after reset. It is not necessary to write

a zero to end the master reset operation. Writing 0s to the reserved bits is suggested.

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