REV. PrD

–6–

PRELIMINARY TECHNICAL DATA

12

PWRGD

Power Good (active high). This is an open drain output pin which, via the assistance of an

external pull-up resistor to the desired voltage, indicates that the core voltage is within the

specified tolerance of the VID programmed value or else in a VID transition state as indicated

by a recent state transition of either the

BOM or DPRSLP pins. PWRGD is deactivated

(pulled low) when the IC is disabled or in UVLO mode or starting up, or the COREFB

voltage is out of the core powergood window. The open drain output allows external wired

ANDing (logical NORing) with other open drain/collector power-good indicators.

13

SD

Shutdown (active low). This is a digital input pin coming from a system signal which, in its

active state, shuts down the IC operation, placing the IC in its lowest quiescent current state

for maximum power savings.

14

CLAMP

Clamp (active high). This is an open drain output pin which, via the assistance of an external

pull-up resistor, indicates that the core voltage should be clamped for its protection. To allow

the highest level of protection, the CLAMP signal is developed using both a redundant

reference and a redundant feedback path with respect to those of the main regulation loop.

The signal is timed out using the softstart capacitor, so an external current protection

mechanism (e.g., fuse or AC adapter's current limit) should be tripped within ~3 times the

programmed soft start time (e.g. 5~10 ms). In a preferred and more conservative configura-

tion, the core voltage is clamped by an external FET. The initial protection function is served

when it is activated by detection of either an over-voltage or a reverse-voltage condition on the

COREFB pin. A backup protection function due to loss of the latched signal at IC power-off

is served by connecting the pull-up resistor to a system "ALWAYS" regulator output (e.g.,

V5_ALWAYS). If the external FET is used, this implementation will keep the core voltage

clamped until the ADP3422 has power re-applied, thus keeping protection for the CPU even

after a hard-failure power-down and restart (e.g., a shorted top or bottom FET).

15

DRVLSD

Drive-Low Shutdown (active low). This is a digital output pin which, in its active state,

indicates that the lower FET of the core VR should be disabled. In the suggested application

schematic this pin is directly connected to the pin of the same name on the ADP3415 or other

driver IC. Drive-low shutdown is normally activated by the DPRSLP signal, corresponding to

a light load condition, but a number of dynamic conditions can override the control of this pin

as needed.

16

SS

Soft Start. This is an analog I/O pin whose output is a controlled current source used to

charge or discharge an external grounded capacitor and whose input is the detected voltage

that is indicative of elapsed time. The pin controls the soft start time of the IC as well as the

hiccup cycle time during overload including but not limited to short circuit, over voltage, and

reverse voltage. Hiccup operation is a feature that was added to reduce short circuit power

dissipation by more than an order of magnitude, while still allowing an automatic restart when

the failure mode ceased. The hiccup operation can be overwritten and changed to latched-off

operation by clamping the SS pin voltage to a voltage level somewhere above ~ 0.2 V. In this

configuration, the controller does not restart after a hiccup cycle is initiated, but stays latched

off.

17

COREFB

Core Feedback. This is a high-impedance analog input pin that is used to monitor the output

voltage for setting the proper state of the PWRGD and CLAMP pins. It is generally recom-

mended to RC-filter the ripple and noise from the monitored core voltage, as suggested by the

application schematic.

18

DACOUT

Digital-to-Analog Converter Output. This output voltage is the VID-controlled reference

voltage whose primary function is to determine the output voltage regulation point.

19

GND

Ground.

20

OUT1

Output to Driver 1. This is a digital output pin which is used to command the state of the

switched node via the driver and MOSFET switches. It should be connected to the IN pin of

the ADP3415 driver that corresponds to the first of two channels.

Pin

Mnemonic

Function

ADP3203