ADP3203 datasheet(2/12 Pages) AD

2 / 12 page

REV. PrD

–2–

PRELIMINARY TECHNICAL DATA

ADP3203–SPECIFICATIONS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

SUPPLY-UVLO-SHUTDOWN

Normal Supply Current

715

UVLO Supply Current

CCUVLO

425

µA

Shutdown Supply Current

CCSD

SD = L, 3.0 V

≤≤≤≤≤ VCC ≤≤≤≤≤ 3.6 V

µA

UVLO Threshold

SD = H

CCH

CC ramping up, VSS= 0 V

2.9

CCL

CC ramping down,

2.65

SS floating

UVLO Hysteresis

CCHYS

Shutdown Threshold (CMOS Input)

SDTH

CC/2

POWERGOOD-CORE FEEDBACK

Core Feedback Threshold Voltage

COREFBH

0.9 V < V

DAC < 1.675 V

COREFB ramping up

1.12 V

DAC

1.14 V

DAC

COREFB ramping down

1.10 V

DAC

1.12 V

DAC

COREFB ramping up

0.88 V

DAC

0.90 V

DAC

COREFB ramping down

0.86 V

DAC

0.88 V

DAC

Power Good Output Voltage

PWRGD

COREFB = VDACOUT

0.95 V

(open drain output)

COREFB = 0.8 VDACOUT

0.8

Masking Time

PWRGD,MSK

CC = 3.3 V

100

µs

SOFT-START/HICCUP TIMER

Charge/Discharge Current

SS = 0 V

–16

µA

SS = 0.5 V

0.5

µA

Soft-Start Enable/Hiccup

REG = 1.25 V,

Termination Threshold

RAMP = VCOREFB = 1.27 V

SSENDWN

SS ramping down

200

SSENUP

SS ramping up

150

Soft-Start Termination/Hiccup

SSTERM

RAMP = VCOREFB = 1.27 V

Enable Threshold

SS ramping up

1.75

2.00

2.25

VID DAC

VID Input Threshold (CMOS Inputs)

VID0..4

CC/2

VID Input Current

VID0..4

VID 0..4 = L

µA

(Internal Active Pull-up)

Output Voltage

DAC

See VID Code Table 1

0.600

1.750

Accuracy

∆V

DAC/VDAC

0.850 V < V

DAC < 1.750 V

–1.0

+1.0

0.600 V < V

DAC < 0.825 V

–8.5

+8.5

Settling Time

DACS

∆V

DAC = 0.5 V, CDAC = 10 nF

3.5

µs

Notes:

1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2 Guaranteed by characterization.

3 Measured from 50% of VID code transition amplitude to the point where V

DACOUT settles within ±1% of its steady state value.

4 40 mV

PP amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to

50% of the output voltage swing.

5 Measured between the 30% and 70% points of the output voltage swing.

6 Two test conditions: 1)PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V

COREFB,BAD = 1.0 V at VVID = 1.25 V setting) to

the COREFB pin right after the moment that

BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking

delay time. 2) PWRGD is forced to fail (V

COREFB,BAD = 1.0 V at VVID = 1.25 V setting) but gets into the CoreGood-window

COREFB,GOOD = 1.25 V) right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified

blanking delay time.

7Guaranteed by design.

( T

===== 25 °C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, V

COREFB =

DAC (

≡ V

DACOUT), VREG = VCS– = VVID = 1.25 V, ROUT = 100 k

Ω

Ω, C

OUT = 10 pF,

SS = 47 nF, RPWRGD = 680

Ω

Ω to 1.2 V, R

CLAMP = 5.1 k

Ω

Ω to VCC, HYSSET, BSHIFT,

DSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted) Current sunk by a pin has a positive sign, sourced by a pin has a

negative sign. Negative sign is disregarded for min and max values.

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