One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel:781/329-4700

www.analog.com

Fax:781/326-8703

©ANALOG DEVICES, INC., 2002

REV. PrD 1/02

a

2-Phase IMVP-II & IMVP-III

Core Controller for Mobile CPUs

Preliminary Technical Data

ADP3203

FEATURES

Pin Selectable 1 or 2-Phase Operation

Backward Compatible to IMVP-II

Excellent Static and Dynamic Current Sharing

Superior Load Transient Response with ADOPT

TM

Optimal Positioning Technology

Noise-Blanking for Speed and Stability

Synchronous Rectifier Control for Extended Battery

Life

Cycle-by-Cycle Current Limiting

Hiccup or Latched Overload Protection

Transient-Glitch-Free Power Good

Soft Start Eliminates Power-On In-Rush Current Surge

Two-Level Over-Voltage and Reverse-Voltage

Protection

APPLICATIONS

IMVP II-III Core DC/DC Converters

Fixed Voltage Mobile CPU Core DC/DC Converters

Notebook/Laptop Power Supplies

Programmable Output Power Supplies

GENERAL DESCRIPTION

The ADP3203 is a 1 or 2-phase hysteretic peak current

DC-DC buck converter controller dedicated to power a

mobile processor's core. The optimized low voltage design is

powered from the 3.3 V system supply and draws only

10 µA maximum in shutdown. The nominal output voltage

is set by a 5-bit VID code. To accommodate the transition

time required by the newest processors for on-the-fly VID

changes, the ADP3203 features high-speed operation to

allow a minimized inductor size that results in the fastest

change of current to the output. To further allow for the

minimum number of output capacitors to be used, the

ADP3203 features active voltage positioning with ADOPT

TM

optimal compensation to ensure a superior load transient

response. The output signal interfaces with the ADP3415

MOSFET driver that is optimized for high speed and high

efficiency for driving both the top and bottom MOSFETs of

the buck converter. The ADP3203 is capable of controlling

the synchronous rectifier to extend battery lifetime in light

load conditions.

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

VID0

VID1

VID2

VID3

VID4

DACOUT

GND

VCC

CS+

CS-

REG

ADP3203

CLIM

CORE

SS

19

COREFB

PWRGD

16

SD

7

BOM

DSLP

DPRSLP

HYSSET

BSHIFT

DSHIFT

HYSTERESIS

SETTING

&

SHIFT-MUX

3

1

25

26

CLAMP

SR CONTROL

COREGD MONITOR

SS-HICCUP TIMER & OCP

OVP & RVP

ENABLE _UVLO MAIN BIAS

PWRGD BLANKER

VID MUX &

SHIFT

SELECTOR

15

11

13

14

2

22

PM MODULE

12

28

27

VR

8

EN

RAMP

24

VR

23

DRVLSD

PHASE

SPLITER

OUT2

OUT1

CURRENT

SENSE

MUX

CS1

CS2

18

21

20

17

10

9

6

5-BIT VID

DAC

&

FIXED

REF

5

4

PRELIMINARY TECHNICAL DATA