CYUSB301X

Document Number: 001-52136 Rev. *N

Page 26 of 45

Table 10. GPIF II Timing in Asynchronous Mode[5, 6]

Note The following parameters assume one state transition

Parameter

Description

Min

Max

Units

tDS

Data In to DLE setup time. Valid in DDR async mode.

2.3

–

ns

tDH

Data In to DLE hold time. Valid in DDR async mode.

2

–

ns

tAS

Address In to ALE setup time

2.3

–

ns

tAH

Address In to ALE hold time

2

–

ns

tCTLassert

CTL I/O asserted width for CTRL inputs without DQ input association

and for outputs.

7

–

ns

tCTLdeassert

CTL I/O deasserted width for CTRL inputs without DQ input associ-

ation and for outputs.

7

–

ns

tCTLassert_DQassert

CTL asserted pulse width for CTL inputs that signify DQ inputs valid

at the asserting edge but do not employ in-built latches (ALE/DLE) for

those DQ inputs.

20

–

ns

tCTLdeassert_DQassert

CTL deasserted pulse width for CTL inputs that signify DQ input valid

at the asserting edge but do not employ in-built latches (ALE/DLE) for

those DQ inputs.

7

–

ns

tCTLassert_DQdeassert

CTL asserted pulse width for CTL inputs that signify DQ inputs valid

at the deasserting edge but do not employ in-built latches (ALE/DLE)

for those DQ inputs.

7

–

ns

tCTLdeassert_DQdeassert

CTL deasserted pulse width for CTL inputs that signify DQ inputs valid

at the deasserting edge but do not employ in-built latches (ALE/DLE)

for those DQ inputs.

20

–

ns

tCTLassert_DQlatch

CTL asserted pulse width for CTL inputs that employ in-built latches

(ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built

latches are always close at the deasserting edge.

7

–

ns

tCTLdeassert_DQlatch

CTL deasserted pulse width for CTL inputs that employ in-built latches

(ALE/DLE) to latch the DQ inputs. In this non-DDR case, in-built

latches always close at the deasserting edge.

10

–

ns

tCTLassert_DQlatchDDR

CTL asserted pulse width for CTL inputs that employ in-built latches

(DLE) to latch the DQ inputs in DDR mode.

10

–

ns

tCTLdeassert_DQlatchDDR

CTL deasserted pulse width for CTL inputs that employ in-built latches

(DLE) to latch the DQ inputs in DDR mode.

10

–

ns

tAA

DQ/CTL input to DQ output time when DQ change or CTL change

needs to be detected and affects internal updates of input and output

DQ lines.

–

30

ns

tDO

CTL to data out when the CTL change merely enables the output flop

update whose data was already established.

–

25

ns

tOELZ

CTL designated as OE to low-Z. Time when external devices should

stop driving data.

0

–

ns

tOEHZ

CTL designated as OE to high-Z

8

8

ns

tCLZ

CTL (non-OE) to low-Z. Time when external devices should stop

driving data.

0

–

ns

tCHZ

CTL (non-OE) to high-Z

30

30

ns

tCTLalpha

CTL to alpha change at output

–

25

ns

tCTLbeta

CTL to beta change at output

–

30

ns

tDST

Addr/data setup when DLE/ALE not used

2

–

ns

tDHT

Addr/data hold when DLE/ALE not used

20

–

ns

Notes

5. All parameters guaranteed by design and validated through characterization.

6. "alpha" output corresponds to "early output" and "beta" corresponds to "delayed output". Please refer to the GPIFII Designer Tool for the use of these outputs.