FX3 datasheet(28/45 Pages) CYPRESS

28 / 45 page

CYUSB301X

Document Number: 001-52136 Rev. *N

Page 28 of 45

Synchronous Slave FIFO Write Sequence Description

■ FIFO address is stable and the signal SLCS# is asserted

■ External master or peripheral outputs the data to the data bus

■ SLWR# is asserted

■ While the SLWR# is asserted, data is written to the FIFO and

on the rising edge of the PCLK, the FIFO pointer is incremented

■ The FIFO flag is updated after a delay of t WFLG from the rising

edge of the clock

The same sequence of events is also shown for burst write

Note For the burst mode, SLWR# and SLCS# are asserted for

the entire duration, during which all the required data values are

written. In this burst write mode, after the SLWR# is asserted, the

data on the FIFO data bus is written to the FIFO on every rising

edge of PCLK. The FIFO pointer is updated on each rising edge

of PCLK.

Short Packet: A short packet can be committed to the USB host

by using the PKTEND#. The external device or processor should

be designed to assert the PKTEND# along with the last word of

data and SLWR# pulse corresponding to the last word. The

FIFOADDR lines must be held constant during the PKTEND#

assertion.

Zero-Length Packet: The external device or processor can

signal a Zero-Length Packet (ZLP) to FX3 simply by asserting

PKTEND#, without asserting SLWR#. SLCS# and address must

be driven as shown in Figure 13 on page 28.

FLAG Usage: The FLAG signals are monitored for flow control

by the external processor. FLAG signals are outputs from FX3

that may be configured to show empty, full, or partial status for a

dedicated thread or the current thread that is addressed.

Figure 13. Synchronous Slave FIFO Write Mode

Synchronous Write Cycle Timing

PCLK

FIFO ADDR

tCYC

tCH

tCL

tAS

SLCS

SLWR

Data IN

High-Z

DN(An)

tDH

tDS tDH

tDS

tDH

tWRS

tWRH

tPEH

PKTEND

DN(Am)

DN+1(Am) DN+2(Am)

SLOE

(HIGH)

tAH

tPES

FLAGA

dedicated thread FLAG for An

(1 = Not Full 0= Full)

tCFLG

FLAGB

current thread FLAG for Am

(1 = Not Full 0= Full)

tCFLG

3 cycle latency from SLWR# to FLAG

3 cycle latency from SLWR # to FLAG

PCLK

FIFO ADDR

tCYC

tCH

tCL

tAS

SLCS

SLWR

(HIGH)

Data IN

High-Z

PKTEND

SLOE

(HIGH)

tAH

FLAGA

dedicated thread FLAG for An

(1 = Not Full 0= Full)

FLAGB

current thread FLAG for Am

(1 = Not Full 0= Full)

tPEH

tPES

Synchronous ZLP Write Cycle Timing

tCFLG

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