AM186 datasheet(44/112 Pages) AMD

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Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

Pseudo Static RAM (PSRAM) Support

The Am186ER and Am188ER microcontrollers support

the use of PSRAM devices in low memory chip-select

(LCS) space only. When PSRAM mode is enabled, the

timing for the LCS signal is modified by the chip-select

control unit to provide a CS precharge period during

PS R A M a cce sse s. T h e 5 0 - M H z t i ming o f t h e

Am186ER and Am188ER microcontrollers is appropri-

ate to allow 70-ns PSRAM to run with one wait state.

PSRAM mode is enabled through a bit in the Low Mem-

ory Chip-Select (LMCS) Register. The PSRAM feature

is disabled on CPU reset.

In addition to the LCS timing changes for PSRAM pre-

charge, the PSRAM devices also require periodic re-

fresh of all internal row addresses to retain their data.

Although refresh of PSRAM can be accomplished sev-

eral ways, the Am186ER and Am188ER microcontrol-

lers implement auto refresh only.

The Am186ER and Am188ER microcontrollers gener-

ate RFSH, a refresh signal, to the PSRAM devices

when PSRAM mode is enabled. No refresh address is

required by the PSRAM when using the auto refresh

mechanism. The RFSH signal is multiplexed with the

MCS3 signal pin. When PSRAM mode is enabled,

MCS3 is not available for use as a chip-select signal.

The refresh control unit must be programmed before

accessing PSRAM in LCS space. The refresh counter

in the Clock Prescaler (CDRAM) Register must be con-

figured with the required refresh interval value. The re-

fresh counter reload value in the CDRAM Register

should not be set to less than 18 (12h) in order to pro-

vide time for processor cycles between refreshes. The

refresh address counter must be set to 000000h to pre-

vent the MCS3–MCS0 or PCS6–PCS0 chip selects

from asserting. UCS may randomly assert during a

PSRAM refresh.

LCS is held High and the A bus is not used during re-

fresh cycles. The LMCS Register must be configured to

external ready ignored (R2 = 1) with one wait state

(R1–R0 = 01b), and the PSRAM mode enable bit (SE)

must be set. The ending address of LCS space in the

LMCS Register must also be programmed.

PERIPHERAL CONTROL BLOCK (PCB)

The integrated peripherals of the Am186ER and

Am188ER microcontrollers are controlled by 16-bit

read/write registers. The peripheral registers are con-

tained within an internal 256-byte control block. The

registers are physically located in the peripheral de-

vices they control, but they are addressed as a single

256-byte block. Figure 9 on page 46 shows a map of

these registers.

Reading and Writing the PCB

Code intended to execute on the Am188ER microcon-

troller should perform all writes to the PCB registers as

byte writes. These writes will transfer 16 bits of data to

the PCB Register even if an 8-bit register is named in

the instruction. For example, out dx, al results in

the ax value being written to the port address in dx.

Reads to the PCB should be done as word reads. Code

written in this manner will run correctly on the

Am188ER and Am186ER microcontrollers.

Unaligned reads and writes to the PCB result in unpre-

dictable behavior on both the Am186ER and Am188ER

microcontrollers.

For a complete description of all the registers in the

PCB, refer to the

Am186ER and Am188ER Microcon-

trollers User’s Manual, order #21684.

CLOCK AND POWER MANAGEMENT

The clock a nd powe r ma na ge me nt un it of th e

Am186ER and Am188ER microcontrollers includes a

phase-locked loop (PLL) and a second programmable

system clock output (CLKOUTB).

Phase-Locked Loop (PLL)

In a traditional 80C186/80C188 design, the internal clock

frequency is half the frequency of the crystal. Because of

the internal PLL on the Am186ER and Am188ER micro-

controllers, the internal clock generated by both micro-

controllers can operate at up to four times the frequency

of the crystal. The Am186ER and Am188ER microcon-

trollers operate in the following modes:

n Divide by Two—Frequency of the system clock is

half the frequency of the crystal with PLL disabled.

n Times One—Frequency of the system clock will be

the same as the external crystal with PLL enabled.

n Times Four—Frequency of the system clock is four

times the frequency of the crystal with PLL enabled.

The default Times Four mode must be used for processor

frequencies above 40 MHz. The Divide by Two mode

should be used for frequencies below 16 MHz. The clock-

ing mode is selected using CLKSEL1 and CLKSEL2 on

reset. Table 8 provides the maximum and minimum fre-

quencies for X1, X2, and CLKOUTA according to clocking

mode.

Table 8.

Maximum and Minimum Clock

Frequencies

Mode

X1/X2

Max

X1/X2

Min

CLKOUTA

Max

CLKOUTA

Min

Divide by 2

40 MHz

30 MHz

20 MHz

15 MHz

Times 1

40 MHz

16 MHz

40 MHz

16 MHz

Times 4

12.5 MHz

4 MHz

50 MHz

16 MHz

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