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AM186 Arkusz danych(PDF) 90 Page - Advanced Micro Devices |
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AM186 Arkusz danych(HTML) 90 Page - Advanced Micro Devices |
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90 / 112 page ![]() 90 Am186TMER and Am188TMER Microcontrollers Data Sheet DRAF T Switching Characteristics over Commercial and Industrial Operating Ranges Software Halt Cycle (25 MHz and 33 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN signal. Switching Characteristics over Commercial and Industrial Operating Ranges Software Halt Cycle (40 MHz and 50 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN signal. Preliminary Parameter 25 MHz 33 MHz No. Symbol Description Min Max Min Max Unit General Timing Responses 3 tCHSV Status Active Delay 0 20 0 15 ns 4 tCLSH Status Inactive Delay 0 20 0 15 ns 5 tCLAV AD Address Invalid Delay 0 20 0 15 ns 9 tCHLH ALE Active Delay 20 15 ns 10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns 11 tCHLL ALE Inactive Delay 20 15 ns 19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns 22 tCHCTV Control Active Delay 2(b) 0 20 0 15 ns 68 tCHAV CLKOUTA High to A Address Invalid 0 20 0 15 ns Preliminary Parameter 40 MHz 50 MHz No. Symbol Description Min Max Min Max Unit General Timing Responses 3 tCHSV Status Active Delay 0 12 0 10 ns 4 tCLSH Status Inactive Delay 0 12 0 10 ns 5 tCLAV AD Address Invalid Delay 0 12 0 10 ns 9 tCHLH ALE Active Delay 12 10 ns 10 tLHLL ALE Width tCLCL–5=20 15 ns 11 tCHLL ALE Inactive Delay 12 10 ns 19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns 22 tCHCTV Control Active Delay 2(b) 0 12 0 10 ns 68 tCHAV CLKOUTA High to A Address Invalid 0 10 0 10 ns |
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