STM32F107VB datasheet(74/103 Pages) STMICROELECTRONICS

74 / 103 page

Electrical characteristics

STM32F105xx, STM32F107xx

74/104

Doc ID 15274 Rev 6

Equation 1: RAIN max formula

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an

error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

tlat

(2)

Injection trigger conversion latency

fADC = 14 MHz

0.214

µs

3(4)

1/fADC

tlatr

(2)

Regular trigger conversion latency

fADC = 14 MHz

0.143

µs

2(4)

1/fADC

(2)

Sampling time

fADC = 14 MHz

0.107

17.1

µs

1.5

239.5

1/fADC

tSTAB

(2)

Power-up time

µs

tCONV

(2) Total conversion time (including

sampling time)

fADC = 14 MHz

µs

14 to 252 (tS for sampling +12.5 for

successive approximation)

1/fADC

Based on characterization, not tested in production.

Guaranteed by design, not tested in production.

VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.

For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 52.

Table 52.

ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 53.

RAIN max for fADC = 14 MHz

(1)

Based on characterization, not tested in production.

Ts (cycles)

tS (µs)

RAIN max (kΩ)

1.5

0.11

0.4

7.5

0.54

5.9

13.5

0.96

11.4

28.5

2.04

25.2

41.5

2.96

37.2

55.5

3.96

71.5

5.11

239.5

17.1

AIN

ADC

()

--------------------------------------------------------------

ADC

–

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