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STM32F107VB Arkusz danych(PDF) 77 Page - STMicroelectronics |
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STM32F107VB Arkusz danych(HTML) 77 Page - STMicroelectronics |
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77 / 103 page  STM32F105xx, STM32F107xx Electrical characteristics Doc ID 15274 Rev 6 77/104 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 36 or Figure 37, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. V REF+ STM32F10xxx V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai14380c (See note 1) (See note 1) VREF+/VDDA STM32F10xxx 1 µF // 10 nF VREF–/VSSA ai14381c (See note 1) (See note 1) |
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