MSC1202Y2RHHT datasheet(65/92 Pages) TI1

65 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

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System Clock Divider (SYSCLK)

Reset Value

SFR C7h

DIVMOD1

DIVMOD0

DIV2

DIV1

DIV0

00h

NOTE: Changing the SYSCLK registers affects all internal clocks, including the ADC clock.

DIVMOD1−0 Clock Divide Mode

bits 5−4

Write:

DIVMOD

DIVIDE MODE

Normal mode (default, no divide).

Immediate mode: start divide immediately; return to Normal mode on Idle mode wakeup condition, or by direct write to SFR.

Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is

enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled,

the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter

overflows, which follows a wakeup condition. Can exit by directly writing to SFR.

Manual mode: start divide immediately; exit mode only by directly writing to SFR. Same as immediate mode, but cannot

return to Normal mode on Idle mode wakeup condition; only by directly writing to SFR.

Read:

DIVMOD

DIVIDE MODE STATUS

No divide

Divider is in Immediate mode

Divider is in Delay mode

Manual mode

DIV2−0

Divide Mode

bit 2−0

DIV

DIVISOR

fCLK FREQUENCY

000

Divide by 2 (default)

fCLK = fSYS/2

001

Divide by 4

fCLK = fSYS/4

010

Divide by 8

fCLK = fSYS/8

011

Divide by 16

fCLK = fSYS/16

100

Divide by 32

fCLK = fSYS/32

101

Divide by 1024

fCLK = fSYS/1024

110

Divide by 2048

fCLK = fSYS/2048

111

Divide by 4096

fCLK = fSYS/4096

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