MSC1202Y2RHHT datasheet(74/92 Pages) TI1

74 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

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Summation 0 (SUMR0)

Reset Value

SFR E2h

LSB

00h

SUMR0

Summation 0. This is the least significant byte of the 32-bit summation register, or bits 0 to 7.

bits 7−0

Write: Will cause values in SUMR3−0 to be added to the summation register.

Read: Will clear the Summation Interrupt.

Summation 1 (SUMR1)

Reset Value

SFR E3h

00h

SUMR1

Summation 1. This is the most significant byte of the lowest 16 bits of the summation register, or bits 8−15.

bits 7−0

Summation 2 (SUMR2)

Reset Value

SFR E4h

00h

SUMR2

Summation 2. This is the most significant byte of the lowest 24 bits of the summation register, or bits 16−23.

bits 7−0

Summation 3 (SUMR3)

Reset Value

SFR E5h

MSB

00h

SUMR3

Summation 3. This is the most significant byte of the 32-bit summation register, or bits 24−31.

bits 7−0

Offset DAC (ODAC)

Reset Value

SFR E6h

00h

ODAC

Offset DAC. This register will shift the input by up to half of the ADC full-scale input range. The Offset DAC

bits 7−0

value is summed into the ADC prior to conversion. Writing 00h or 80h to ODAC turns off the Offset DAC. The offset

DAC should be cleared prior to calibration, since the offset DAC analog output is applied directly to the ADC input.

bit 7

Offset DAC Sign Bit.

0 = Positive

1 = Negative

bit 6−0

Offset

REF

@ PGA @

ODAC [ 6 : 0]

127

@ (*1)

bit7

NOTE: ODAC cannot be used to offset the analog inputs so that the buffer can be used for signals within 50mV of AGND.

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