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ICSSSTV16859

Preliminary Product Preview

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General Description

Pin Configuration

The 13-bit to 26-bit ICSSTV16859 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2

I/O Levels except for the RESET# input which is LVCMOS.

Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the

positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS

levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and

when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and

clock are switched off.

The ICSSSTV16859 supports low-power standby operation. When RESET# is LOW, the differential input receivers

are disabled, and are allowed. In addition, when RESET# is LOW, all registers are reset, and all outputs are forced

LOW. The LVCMOS RESET# input must always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the

LOW state during power up.

In the DDR DIMM application RESET# is specified to be completely asynchronous with respect to CK and CK#.

Therefore, no timing relationship can be guaranteed between the two. When entering RESET#, the register will be

cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers,

thus ensuring no glitches on the output. However, when coming out of RESET#, the register will become active

quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock

is stable, during the time from the LOW-to-HIGH transition of RESET# until the input receivers are fully enabled, the

design must ensure that the outputs will remain LOW.

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