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ICSSSTV16859 Arkusz danych(PDF) 5 Page - Integrated Circuit Systems

Numer części ICSSSTV16859
Szczegółowy opis  DDR 13-Bit to 26-Bit Registered Buffer
PDF  8 Pages
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Producent  ICST [Integrated Circuit Systems]
Strona internetowa  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICSSSTV16859 Arkusz danych(HTML) 5 Page - Integrated Circuit Systems

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ICSSSTV16859
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Timing Requirements
(over recom mended operating free-air temperature range, unless otherwise noted)
MIN
M AX
fclock
Clock frequency
200
M Hz
t
PD
Clock to output time
TBD
ns
tRST
Reset to outp ut time
5
ns
tSL
Outpu t slew rate
1
4
V/ns
Setup time, fast slew rate 2, 4
0.75
ns
Setup time, slow slew rate 3, 4
0.9
ns
Hold time, fast slew rate 2, 4
0.75
ns
Hold time, slow slew rate 3, 4
0.9
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate=≥ 1V/ns.
4 - CLK, CLK# signals input slew rates are=≥=1V/ns.
SYM BOL
tSU
Th
Note s:
3 - For data signal input slew rate=≥=0.5V/ns and < 1V/ns.
VDD = 2.5V ±0.2V
UNITS
PARAM ETERS
Data before C K
↑ , CK#↓
Data after CK
↑ , CK#↓
Switching Characteristics
(over recomm ended operating free-air temperature range, unless otherwise noted)
MIN
TYP
M AX
fmax
200
M Hz
tPD
C LK, CLK#
Q
1.1
2.8
ns
tph1
C LK, CLK#
Q
5
ns
SYM BOL
VDD = 2.5V ±0.2V
UNITS
From
(Input)
To
(Output)



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