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INTERRUPT HANDLING FOR STR7 MICROCONTROLLERS

When the IVR register is read, this informs the EIC that this interrupt is being processed, the

IRQ line to the ARM core is asserted high. The details of the previous request need to be held

so that processing can be resumed. Firstly, the EIC saves the value of the Current Interrupt

Priority Register (CIPR) in the EIC Interrupt Priority in the Priority Stack, then updates CIPR

with the new priority level. The priority stack can hold up to 16 entries.

Once the current interrupt being processed has finished, the related bit in the IPR register has

to be cleared by software, the previous one can be restored for processing. The Priority level

is restored back from the stack to CIPR, the channel ID is returned back and IVR creates the

previous Interrupt Vector.

6.2 EIC METHODS

Several methods may be defined for the EIC to handle an IRQ interrupt, this application note

will focus on three of them. These methods may be used for pointing a IRQ handler and de-

pends on the IVR register content.

The first is the address method where a simple address is placed in IVR. For example, an IRQ

handler can be placed on an appropriate address boundary pointed to directly by the direct

memory address in IVR. The IVR[31:16] will contain the MSB of the interrupt handler address,

while the SIR[31:16] will contain the LSB. In this case, an interrupt handler has to be located

within 64KBytes starting from the base address defined in the IVR[31:16]. If IVR[31;16] =

0x6000, the first IRS may start at address 0x60000000, and the last one should start, at least,

from address 0x6000FFFC.

Secondly, the Branch method puts a Branch instruction and IRQ handler where the handler is

within the 32MBytes Branch instruction range. The IVR[31:16] will contain the MSB of the

Branch instruction, while the SIR[31:16] will contain the Branch offset.

Lastly, the LDR PC method, a LDR pc,[pc,#offset] instruction can be used to set the program

counter to load the value of an address nearby, where the address itself can be for a handler

which is outside the 32Mbytes branch instruction range.

Note: when an EIC method is used, this will be fixed for all the interrupt channels.

6.3 NESTED INTERRUPT

Since the EIC manages the interrupt priority and automatic vectorization, nested interrupts are

possible, however care must be taken to ensure that the system state is preserved when han-

dling interrupts. For example, it is possible that the system state is lost if another interrupt pre-

empts the current one when storing the link register (lr_irq) and the saved program status reg-

ister (spsr_irq).

The issue lies in the fact that if care is not taken to correctly preserve the return address in the

lr_irq register and the spsr_irq register contents, they may get corrupted if a second interrupt