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AN2979 Arkusz danych(PDF) 3 Page - STMicroelectronics |
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AN2979 Arkusz danych(HTML) 3 Page - STMicroelectronics |
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3 / 12 page ![]() AN2979 Application description Doc ID 15651 Rev 1 3/12 1 Application description 1.1 Comparator features The STM8L101xx microcontroller embeds two zero-crossing comparators sharing the same current bias and the same voltage reference. This voltage reference can be: ● internal (comparison to ground) ● or external (comparison to a reference pin voltage) Each comparator is connected to 4 channels which can be used to generate an interrupt, a timer input capture or a timer break. Their polarity can be inverted. Note: For external comparison be aware that the STM8L101xx comparator maximum input value is VDD -1.25 V with VDDmax = 3.6 V 1.2 ADC implementation Each comparator can be used to implement an ADC. This technique is based on a simple principle: the signal to be measured is connected to the non-inverted input and the reference signal is an external signal connected to the inverting input. In the demonstration software, the comparator used is COMP2 and the channel used as the signal to be measured is the channel 3 (pin PD2). The reference signal is generated by charging a capacitor through a resistor. While the voltage across the capacitor is being charged, it follows an exponential curve. This exponential equation has been implemented in the software. The time taken by the capacitor voltage to rise above the voltage value to be converted is used in the charge equation to retrieve the digital conversion value. Charge equation: Where: ● Vmeas is the value to be mesaured ● VDD is the input voltage ● t is the time measured by timer2 when the comparator detects that the input voltage is above the reference voltage ● T is the RC constant (here R=10 k Ω and C=100 nF so T= 1 ms) The capacitor is charged and discharged using the timer 2 PWM on channel1/ PB0. A timer is programmed to generate a 2 ms PWM with a duty cycle of 0.25. This 2-ms period permits an ADC implementation using the full voltage range that the comparator tolerates. The capacitor charging curve is shown in the following figure. V meas V DD 1 t T --- – ⎝⎠ ⎛⎞ exp – ⎝⎠ ⎛⎞ × = |
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