UM0851 datasheet(32/245 Pages) STMICROELECTRONICS

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Platform section

UM0851

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Doc ID 16604 Rev 2

3.2.1

Hardware overview

Each ARM subsystem of the SPEAR family has a Daisy-Chained ARM PrimeCell® vector

interrupt controller (PL190). The VIC provides a software interface to the interrupt system. In

a system with an interrupt controller, software must determine the source requesting service

and where its service routine is loaded. A VIC does both of these in hardware. It supplies

the starting address, or vector address of the service routine corresponding to the highest

priority requesting interrupt source.

The following table shows the differences between the hardware features for SPEAr600 and

SPEAr300.

The main features of the VIC are listed below:

●

Generation of both fast interrupt request (FIQ) and interrupt request (IRQ), according to

ARM system operation. IRQ is used for general interrupts, whereas FIQ is intended for

fast, low-latency interrupt handling. In particular, using a single FIQ source at a time

provides interrupt latency reduction, because the ISR can be directly executed without

determining the source of the interrupt.

●

Support for 16 vectored interrupts (IRQ only). Each vectored interrupt block receives

the IRQ from the interrupt request logic block and generates a vectored interrupt. Each

vectored interrupt is associated with the 32-bit address of the interrupt service routine

to be executed.

●

Hardware interrupt priority, where FIQ interrupt has the highest priority, followed by

vectored IRQs (from vector 0 to vector 15), and then non-vectored IRQs with the lowest

priority.

●

Interrupt masking

●

Interrupt request status and raw interrupt status (prior to masking).

The interrupt inputs must be level sensitive, active high, and held asserted until the interrupt

service routine clears the interrupt. Edge-triggered interrupts are not compatible.

Table 11.

Differences between SPEAr600 and SPEAr300

SPEAr600

SPEAr300

– Two daisy chained ARM PrimeCells

– One ARM PrimeCell

– A total of 64 interrupt lines are available for

each CPU from its two daisy-chained ICs.

– A total of 32 interrupt lines are available for the

CPU from the ARM PrimeCell.

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